參數(shù)資料
型號： NT5SV8M16FT-75BI
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 MM, PLASTIC, TSSOP2-54
文件頁數(shù)： 7/65頁
文件大小： 739K
代理商： NT5SV8M16FT-75BI
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
15
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs
must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-
sented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
COMMAND
NOP
WRITE A
READ B
NOP
tCK2, DQs
CAS latency = 2
DIN A0
tCK3, DQs
CAS latency = 3
DIN A0
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
(Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
相關(guān)PDF資料
PDF描述
NT5TU64M16DG-3C 64M X 16 DDR DRAM, 0.45 ns, PBGA84
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT5SV8M16HS-6K 制造商:Nanya Technology Corporation 功能描述:DRAM
NT5SV8M8DT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV8M8DT-6K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV8M8DT-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV8M8DT-7K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM
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