
NT5SV8M16FS / NT5SV8M16FT
128Mb Synchronous DRAM
REV 1.4
08/2009
38
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Clock and Clock Enable Parameters
Symbol
Parameter
-6K/6KI
-75B/75BI
Units
Notes
Min.
Max.
Min.
Max.
tCK3
Clock Cycle Time, CAS Latency = 3
6
—
7.5
—
ns
tCK2
Clock Cycle Time, CAS Latency = 2
10
—
10
—
ns
tAC3 (A)
Clock Access Time, CAS Latency = 3
—
5
—
5.4
ns
1
tAC2 (A)
Clock Access Time, CAS Latency = 2
—
6
—
6
ns
1
tCKH
Clock High Pulse Width
2.5
—
2.5
—
ns
tCKL
Clock Low Pulse Width
2.5
—
2.5
—
ns
tCES
Clock Enable Set-up Time
1.5
—
1.5
—
ns
tCEH
Clock Enable Hold Time
1.0
—
0.8
—
ns
tSB
Power down mode Entry Time
0
6
0
7.5
ns
tT
Transition Time (Rise and Fall)
0.3
8
0.5
10
ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
Common Parameters
Symbol
Parameter
-6K/6KI
-75B/75BI
Units
Notes
Min.
Max.
Min.
Max.
tCS
Command Setup Time
1.5
—
1.5
—
ns
tCH
Command Hold Time
0.8
—
0.8
—
ns
tAS
Address and Bank Select Set-up Time
1.5
—
1.5
—
ns
tAH
Address and Bank Select Hold Time
0.8
—
0.8
—
ns
tRCD
RAS to CAS Delay
18
—
20
—
ns
1
tRC
Bank Cycle Time
60
—
67.5
—
ns
1
tRAS
Active Command Period
42
100K
45
100K
ns
1
tRP
Precharge Time
18
—
20
—
ns
1
tRRD
Bank to Bank Delay Time
12
—
15
—
ns
1
tCCD
CAS to CAS Delay Time
1
—
1
—
CK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
-6K/6KI
-75B/75BI
Units
Min.
Max.
Min.
Max.
tRSC
Mode Register Set Cycle Time
12
—
15
—
ns