參數(shù)資料
型號(hào)： NT512T64U88B0BY-3C
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 473K
代理商： NT512T64U88B0BY-3C
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
16
03/2007
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.8V ± 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-4200
(-37B)
PC2-5300
(-3C)
PC2-6400
(-25D)
PC2-6400
(-25C)
Unit
I DD0
Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
340
360
400
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC
(MIN);
CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs
changing once per clock cycle
380
420
460
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE
≤ VIL (MAX); tCK = tCK (MIN)
28
mA
I DD2N
Idle Standby Current: CS
≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK =
tCK (MIN); address and control inputs changing once per clock cycle
160
200
204
mA
I DD2Q
Precharge standby current; All banks idle; tCK = tCK (IDD); CKE is high; CS
is high; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
140
160
180
mA
I DD3PF
Active Power-Down Standby Current: one bank active; power-down mode;
CKE
≤ VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA
112
132
156
mA
I DD3PS
Active Power-Down Standby Current: one bank active; power-down mode;
CKE
≤ VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA
36
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS
≥ VIH (MIN); CKE ≥
VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock
cycle
172
200
240
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)
540
640
680
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA
560
640
700
mA
I DD5
Auto-Refresh Current: tRC = tRFC (MIN)
600
640
700
mA
I DD6
Self-Refresh Current: CKE
≤ 0.2V
28
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; tRC = tRC (min); IOUT = 0mA.
1040
1080
mA
Note:
Module IDD was calculated from component IDD. It may differ from the actual measurement.
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