參數(shù)資料
型號: NT2GT72U4PD0BV-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 1/27頁
文件大?。?/td> 648K
代理商: NT2GT72U4PD0BV-3C
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
REV 1.1
1
01/2009
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Based on DDR2-667/800 128Mx8 (1GB/2GB) and 256MX4 (2GB/4GB) SDRAM D-Die
Features
1GB/2GB: 128Mx72/256Mx72 Registered DDR2 DIMM based
on 128Mx8 DDR2 SDRAM. (NT5TU128M8DE)
2GB/4GB: 256Mx72/512MX72 Registered DDR2 DIMM based
on 256Mx4 DDR2 SDRAM. (NT5TU256M4DE)
240-Pin Registered Dual In-Line Memory Module (RDIMM)
Error Check Correction (ECC) Support
Phase-lock loop (PLL) clock driver to reduce loading
Performance:
PC2-5300 PC2-6400
Speed Sort
-3C
-AD
DIMM
Latency
5
6
Unit
fck – Clock Freqency
333
400
MHz
tck – Clock Cycle
3
2.5
ns
fDQ – DQ Burst Freqency
667
800
Mbps
Intended for 333MHz & 400MHz applications
Inputs and outputs are SSTL-18 compatible
VDD = 1.8Volt ± 0.1Volt, VDDQ = 1.8Volt ± 0.1Volt
SDRAMs have 8 internal banks for concurrent operation
One clock cycle added for registered DIMMs to account for
input register
Differential clock inputs
Off-Chip Driver (OCD) Impedance Adjustment
On Die Termination
Data is read or written on both clock edges
Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
Programmable Operation:
- Device
Latency: 3,4,5,6
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
14/11/2 (row/column/rank) Addressing for 4GB
14/11/1 (row/column/rank) Addressing for 2GB
14/10/1 (row/column/rank) Addressing for 1GB/2GB
Serial Presence Detect
Gold contacts
SDRAMs in 60-ball BGA Package
RoHS Complianc
Description
NT1GT72U89D0BV, NT2GT72U4PD0BV, NT2GT72U8PD0BV and NT4GT72U4ND0BV are Registered 240-Pin Double Data Rate 2
(DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one rank 128Mx72, 256Mx72 high-speed memory
array and two ranks 512MX72 high-speed memory array. The module uses nine 128Mx8 (NT1GT72U89D0BV), eighteen 128Mx8
(NT2GT72U8PD0BV), eighteen 256Mx4 (NT2GT72U4PD0BV) and thirty-six 256Mx4 (NT4GT72U4ND0BV) DDR2 SDRAMs in BGA
packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these
common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 333 MHz (or 400 MHz) clock speeds and achieves high-speed data transfer
rates of up to 667Mbps (or 800Mbps ). Prior to any access operation, the device
latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
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