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參數(shù)資料
| 型號： | NS32491 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Network Interface |
| 中文描述： | 串行網(wǎng)絡(luò)接口 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 175K |
| 代理商： | NS32491 |
5.0 Pin Descriptions
Pin No.
Name
I/O
Description
1
COL
O
Collision Detect Output.
A TTL/MOS level active high output. A 10 MHz
(
a
25%–15%) signal at the collision input will produce a logic high at COL
output. When no signal is present at the collision input, COL output will go low.
2
RXD
O
Receive Data Output
. A TTL/MOS level signal. This is the NRZ data output
from the digital phase-locked loop. This signal should be sampled by the
controller at the rising edge of receive clock.
3
CRS
O
Carrier Sense
. A TTL/MOS level active high signal. It is asserted when valid
data from the transceiver is present at the receive input. It is de-asserted one
and a half bit times after the last bit at receive input.
4
RXC
O
Receive Clock
. A TTL/MOS level recovered clock. When the phase-locked loop
locks to a valid incoming signal a 10 MHz clock signal is activated on this output.
This output remains low during idle (5 bit times after activity ceases at receive
input).
5
SEL
I
Mode Select.
A TTL level input. When high, transmit
a
and transmit
b
outputs
are at the same voltage in idle state providing a ‘‘zero’’ differential. When low,
transmit
a
is positive with respect to transmit
b
in idle state.
6
GND
Negative Supply Pin.
7
LBK
I
Loopback
. A TTL level active high on this input enables the loopback mode.
8
X1
I
Crystal or External Frequency Source Input (TTL).
9
X2
O
Crystal Feedback Output
. This output is used in the crystal connection only. It
must be left open when driving X1 with an external frequency source.
10
TXD
I
Transmit Data
. A TTL level input. This signal is sampled by the SNI at the rising
edge of transmit clock when transmit enable input is high. The SNI combines
transmit data and transmit clock signals into a Manchester encoded bit stream
and sends it differentially to the transceiver.
11
TXC
O
Transmit Clock
. A TTL/MOS level 10 MHz clock signal derived from the 20
MHz oscillator. This clock signal is always active.
12
TXE
I
Transmit Enable
. A TTL level active high data encoder enable input. This signal
is also sampled by the SNI at the rising edge of transmit clock.
13
14
TX
b
TX
a
O
Transmit Output
. Differential line driver which sends the encoded data to the
transceiver. These outputs are source followers and require 270
X
pulldown
resistors to GND.
15
16
NC
No Connection.
17
CAP
O
Bypass Capacitor
. A ceramic capacitor (greater than 0.001
m
F) must be
connected from this pin to GND.
18
19
VCC
Positive Supply Pins
. A 0.1
m
F ceramic decoupling capacitor must be
connected across VCC and GND as close to the device as possible.
20
NC
No Connection.
21
22
RX
b
RX
a
I
Receive Input
. Differential receive input pair from the transceiver.
23
24
CD
b
CD
a
I
Collision Input
. Differential collision input pair from the transceiver.
4
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