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參數資料
| 型號： | NJU26118 |
| 廠商： | New Japan Radio Co., Ltd. |
| 英文描述： | NJU26100 Series Hardware Specification |
| 中文描述： | NJU26100系列硬件規(guī)格 |
| 文件頁數： | 4/17頁 |
| 文件大?。?/td> | 270K |
| 代理商： | NJU26118 |
NJU26100 Series
- 4 -
Ver.2005-02-24
1.2 Electric Characteristics
Table1-2 Electric Characteristics
(V
DDO
=V
DDC
=V
DDR
=2.5V, V
SSO
=V
SSC
=V
SSR
=0V, Ta=25
°
C
)
Parameter
Symbol
Operating V
DD
Voltage
V
DD
Operating Current
I
DD
Test Condition
V
DDO
, V
DDC
, V
DDR
pin
f
OSC
=36.864MHz
Min.
2.25
-
Typ.
2.5
40
Max.
2.75
-
Units
V
mA
Operating Temperature
Recommended Operating
Temperature
High Level Input
Voltage (XI)
High Level Input Voltage
Low Level Input Voltage
T
OPR
-40
25
85
°
C
T
OPRR
V
DDO
=V
DDC
=V
DDR
=2.5V
-10
25
70
°
C
V
IH(OSC)
XI pin
2.0
-
V
DD
V
V
IH
V
IL
V
SS
=V
SSO
=V
SSC
=V
SSR
V
IN
=3.3V
expect for GPIO pin
V
IN
=3.3V
GPIO pin Only
V
IN
=V
SSO
=V
SSC
=V
SSR
I
OH
=-2mA
I
OH
=-100
μ
A
I
OL
=2mA
except for SCL/SCK,
SDA/SDOUT,
AD1/SDIN, AD2/SS
ｂ
pin*
1
XI pin
XI pin
2.0
V
SS
-
-
3.3
0.5
V
V
High Level Input Current
I
IH
-10
-
+10
μ
A
High Level Input Current
I
IH(pd)
100
-
300
μ
A
Low Level Input Current
I
IL
-10
-
+10
μ
A
High Level Output Voltage
V
OH
V
DD
-0.4
V
DD
-0.1
-
-
-
-
V
Low Level Output Voltage
Input Capacitance
V
OL
C
IN
-
5
0.4
-
V
pF
Input Rise/Fall transition Time
t
r
/ t
f
-
-
100
ns
Clock Frequency
Ext.System Clock Duty Cycle
*
1
The tr / tf of these pins are specified separately.
*
2
All input / input-and-output pins serve as the Schmidt trigger input except for XI pin.
Input pin
(GPIO0, SCL/SCK, SDA/SDOUT,
AD1/SDIN, AD2/SSb, RESETb, GPIO1,
SDI0, SDI1, SDI2, LRI, BCKI pin)
Fig.1- 1 I/O Equivalent Circuits
*
3
SDA becomes Open-Drain at the time of the output of I
2
C.
f
OSC
r
EC
-
-
38.0
52.5
MHz
%
47.5
50
Output pin
(SDO0, SDO1, SDO2, GPIO0,
*
3
SDA/SDOUT, GPIO1, MCK,
BCKO, LRO pin)
XI / XO pin
(XI, XO)
Input
pin
V
DDR
VDDC
V
SSC
V
DDR
V
SSR
Output
pin
V
DDC
V
DDO
XO
pin
V
SSO
V
SSC
XI
pin
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