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參數(shù)資料
| 型號： | NIS5102 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 脈沖抑制器 |
| 英文描述： | High Side SMART HotPlug IC/Inrush Limiter/Circuit Breaker(高邊SMART熱插拔電路/浪涌電流限制器/電路保護器) |
| 中文描述： | 高端智能熱插拔集成電路/浪涌限制器/斷路器（高邊智能熱插拔電路/浪涌電流限制器/電路保護器） |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 142K |
| 代理商： | NIS5102 |
NIS5102
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS
(continued)
(V
CC
= 12 V, R
LIMIT
= 36 , C
Charge
= 100 pF, T
J
= 25
°
C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
CURRENT LIMIT
Current Limit (Short Circuit, R
LIMIT
= 36 )
I
LIM1
3.8
4.8
5.8
A
Current Limit (Overload, R
LIMIT
= 36 ) (Note 3)
I
LIM2
7.0
7.8
8.6
A
ENABLE/TIMER
Enable Voltage (TurnOn)
V
ENon
2.2
V
Enable Voltage (TurnOff)
V
ENoff
1.6
V
Charging Current (Into External Capacitor)
I
Charge
65
77
88
A
Turnon Delay (Time from Enable High to I
source
= 100 mA)
t
delay
2.2
ms
CHARGE PUMP
C
Charge
(Voltage on Pin 5 with Respect to Ground)
V
CC
= 18 Vdc
V
Ccharge
18
26
V
V
POWER GOOD
Power Good
→
High Z Signal when FET is Fully Enhanced
Low Z State Output Voltage (I
Sink
= 2 mA)
Vpin7
230
300
mV
Leakage Current (Vpin7 = 12 V, High Z State)
I
Leak
2.0
10
A
Power Good Delay
(Time from Power FET is Fully Enhanced to Power Good FET Changing State)
t
pwrgood
15
ms
TOTAL DEVICE
Bias Current (Operational, V
CC
= 12 V)
I
Bias
1.3
2.0
mA
Bias Current (Nonoperational, V
CC
= 7 V))
I
Bias
400
700
A
Minimum Operating Voltage
Vcc
min
8.5
9.0
V
Enable/Timer
Threshold
Input
Source Voltage
Output Current
Figure 2. Timing Diagram for External Enabled Delay
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