參數(shù)資料
型號(hào)： NCT214MT3R2G
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC10
封裝： 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, WQFN-10
文件頁(yè)數(shù)： 13/19頁(yè)
文件大?。?/td> 269K
代理商： NCT214MT3R2G
NCT214
http://onsemi.com
3
PIN ASSIGNMENT
Pin No.
Mnemonic
Description
1
ADD1
Address 1 pin. Tristate input to set the SMBus address.
2
VDD
Positive Supply, 3.0 V to 3.6 V.
3
D+
Positive Connection to Remote Temperature Sensor.
4
D
Negative Connection to Remote Temperature Sensor.
5
THERM
Activelow opendrain overtemperature output pin; needs pullup resistor.
6
GND
Ground.
7
ALERT/THERM2
OpenDrain Logic Output used as interrupt or SMBus ALERT. This can also be configured as a
second THERM output. Requires pullup resistor.
8
SDATA
Logic Input/Output, SMBus Serial Data. OpenDrain Output. Requires pullup resistor.
9
SCLK
Logic Input, SMBus Serial Clock. Requires pullup resistor.
10
ADD0
Address 0 pin. Tristate input to set the SMBus address.
SMBus/I2C TIMING SPECIFICATIONS (Note 1)
Parameter
Limit at TMIN and TMAX
Unit
Description
fSCLK
400
kHz max
tLOW
1.3
ms min
Clock low period, between 10% points.
tHIGH
0.6
ms min
Clock high period, between 90% points.
tR
300
ns max
Clock/data rise time.
tF
300
ns max
Clock/data fall time.
tSU; STA
600
ns min
Start condition setup time.
tHD; STA (Note 2)
600
ns min
Start condition hold time.
tSU; DAT (Note 3)
100
ns min
Data setup time.
tSU; STO (Note 4)
600
ns min
Stop condition setup time.
tBUF
1.3
ms min
Bus free time between stop and start conditions.
1. Guaranteed by design, but not production tested.
2. Time from 10% of SDATA to 90% of SCLK.
3. Time for 10% or 90% of SDATA to 10% of SCLK.
4. Time for 90% of SCLK to 10% of SDATA.
Figure 2. Serial Bus Timing
SCLK
SDATA
tR
tF
tLOW
tHD;DAT
tHD;STA
tHIGH
tSU;DAT
STOP START
STOP
START
tSU;STA
tSU;STO
tHD;STA
tBUF
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