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參數(shù)資料
| 型號(hào)： | NCP5322ADWR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
| 中文描述： | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, SOIC-28 |
| 文件頁(yè)數(shù)： | 8/31頁(yè) |
| 文件大小： | 726K |
| 代理商： | NCP5322ADWR2G |
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NCP5322A
http://onsemi.com
8
ELECTRICAL CHARACTERISTICS (continued)
(0
°
C < T
A
< 70
°
C; 0
°
C < T
J
< 125
°
C; 9.0
V < V
CCH1
= V
CCH2
< 20 V; 4.5 V <
V
CCL
= V
CCL1
= V
CCL2
< 14
V; C
GATE
= 3.3
nF, R
R(OSC)
= 32.4
k , C
COMP
= 1.0
nF, C
REF
= 0.1 F, C
SS
= 0.1 F,
DAC Code 10000 (1.45 V), C
VCC
= 1.0
F; unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
General Electrical Specifications
V
CCH1
or V
CCH2
Operating Current
V
FB
= COMP (no switching)
3.2
4.5
mA
V
CCL
Start Threshold
GATEs switching, Soft Start charging
4.05
4.3
4.5
V
V
CCL
Stop Threshold
GATEs stop switching, Soft Start discharging
3.75
4.1
4.35
V
V
CCL
Hysteresis
GATEs not switching, Soft Start not charging
100
200
300
mV
V
CCH1
Start Threshold
GATEs switching, Soft Start charging
1.8
2.0
2.2
V
V
CCH1
Stop Threshold
GATEs stop switching, Soft Start discharging
1.55
1.75
1.90
V
V
CCH1
Hysteresis
GATEs not switching, Soft Start not charging
100
200
300
mV
Reference Output
V
REF
Output Voltage
0
mA < I(V
REF
) < 1.0
mA
3.2
3.3
3.4
V
Internal Ramp
Ramp Height @ 50% PWM
DutyCycle
CS1 = CS2 = CS
REF
.
125
mV
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
SO28L
1
COMP
Output of the error amplifier and input for the PWM
comparators.
2
V
FB
Voltage Feedback Pin. To use Adaptive Voltage Positioning
(AVP) select an offset voltage at light load and connect a
resistor between V
FB
and V
OUT
. The input current of the V
FB
pin and the resistor value determine output voltage offset for
zero output current. Short V
FB
to V
OUT
for no AVP.
3
V
DRP
Current sense output for AVP. The offset of this pin above the
DAC voltage is proportional to the output current. Connect a
resistor from this pin to V
FB
to set amount AVP or leave this
pin open for no AVP. This pin’s maximum working voltage is
2.3 Vdc.
45
CS1CS2
Current sense inputs. Connect current sense network for the
corresponding phase to each input. The input voltages to
these pins must be kept within 105 mV of CS
REF
or pulse
bypulse current limit will be tripped.
6
CS
REF
Reference for Current Sense Amplifiers, input to the Power
Good comparators, and fast feedback connection to the
PWM comparator. To balance input offset voltages between
the inverting and noninverting inputs of the Current Sense
Amplifiers, connect a resistor between CS
REF
and the output
voltage. The value should be 1/3 of the value of the resistors
connected to the CSx pins. The input voltage to this pin must
not exceed the maximum DAC (VID) setting by more than
100 mV or the internal PWM comparator may saturate.
7
PWRGD
Power Good Output. Open collector output goes low when
CS
REF
(V
OUT
) is out of regulation.
812
V
ID4
V
ID0
Voltage ID DAC inputs. These pins are internally pulled up to
3.3
V if left open.
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| NCP5331 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase PWM Controller with Integrated Gate Drivers |
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