參數(shù)資料
型號(hào)： NCP5314FTR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Two/Three/Four−Phase Buck CPU Controller
中文描述： SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQFP32
封裝： LEAD FREE, LQFP-32
文件頁(yè)數(shù)： 21/29頁(yè)
文件大?。?/td> 684K
代理商： NCP5314FTR2G
NCP5314
http://onsemi.com
21
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
inductor. Also, for an inexpensive iron powder core, such as
the 26 or 52 from Micrometals, the inductance “swing”
with DC bias must be taken into account and inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
6. MOSFET and Heatsink Selection
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the nonoverlap
time of the gate drivers.
+
+
Vi
12 V
Li
TBD
N
Ci
×
Ci
ESR
Ci
/N
Ci
Q2
Q1
Lo
ESR
Co
/N
Co
14 u(t)
N
Co
×
Co
Vi(t = 0) = 12 V
SWNODE
Vo(t = 0) = 1.745 V
V
Ci
I
Lo
V
OUT
I
Li
MAX dI/dt occurs in
first few PWM cycles.
Figure 25. Calculating the Input Inductance
+
I
D
V
GATE
V
DRAIN
Q
GD
Q
GS2
Q
GS1
V
GS_TH
Figure 26. MOSFET Switching Characteristics
For the upper or control MOSFET, the power dissipation
can be approximated from:
(IRMS,CNTL2
(ILo,MAX
QswitchIg
(Qoss2
VIN
fSW)
PD,CONTROL
RDS(on))
VIN
(VIN
fSW)
QRR
fSW)
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the loss associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
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