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參數(shù)資料
| 型號： | NCP5314FTR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two/Three/Four−Phase Buck CPU Controller |
| 中文描述： | SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 684K |
| 代理商： | NCP5314FTR2G |
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NCP5314
http://onsemi.com
16
Figure 20. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50
μ
s/div)
The waveforms in Figure 20 show a simulation of the
current sense signal and the actual inductor current during a
positive step in load current with values of L = 500 nH,
R
L
= 1.6 m
Ω
, R
CSx
= 20 k
Ω
and C
CSx
= .01 F. In this case,
ideal current signal compensation would require R
CSx
to be
31 k
Ω
. Due to the faster than ideal RC time constant, there is
an overshoot of 50% and the overshoot decays with a 200 s
time constant. With this compensation, the I
LIM
pin threshold
must be set more than 50% above the full load current to avoid
triggering current limit during a large output load step.
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients.
Adaptive voltage positioning can reduce peakpeak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is applied. Similarly, the output
voltage can be set lower than nominal during heavy loads to
reduce overshoot when the load current is removed. For low
current applications, a droop resistor can provide fast,
accurate adaptive positioning. However, at high currents,
the loss in a droop resistor becomes excessive. For example,
a 50 A converter with a 1 m
Ω
resistor would provide a
50 mV change in output voltage between no load and full
load and would dissipate 2.5 W.
Lossless adaptive voltage positioning (AVP) is an
alternative to using a droop resistor, but it must respond to
changes in load current. Figure 21 shows how AVP works.
The waveform labeled “normal” shows a converter without
AVP. On the left, the output voltage sags when the output
current is stepped up and later overshoots when current is
stepped back down. With fast (ideal) AVP, the peaktopeak
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded.
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer to
the application diagram in Figure 1). The noload positioning
is now set internally to VID 20 mV, reducing the potential
error due to resistor and bias current mismatches.
In order to realize the AVP function, a resistor divider
network is connected between V
FB
, V
DRP
and V
OUT
.
During noload conditions, the V
DRP
pin is at the same
voltage as the V
FB
pin. As the output current increases, the
V
DRP
pin voltage increases proportionally. This drives the
V
FB
voltage higher, causing V
OUT
to “droop” according to
a loadline set by the resistor divider network.
The response during the first few microseconds of a load
transient is controlled primarily by power stage output
impedance, and by the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
ramp size is too large or the error amp too slow, there will be
a long transition to the final voltage after a transient. This
will be most apparent with low capacitance output filters.
Adaptive Positioning
Limits
Adaptive Positioning
Normal
Fast
Slow
Figure 21. Adaptive Voltage Positioning
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V
2
control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This results in a “crowbar” action to
clamp the output voltage and prevent damage to the load.
The regulator will remain in this state until the fault latch is
reset by cycling power at the V
CC
pin.
Power Good
According to the latest specifications, the Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 22.
The PWRLS pin is provided to allow the PWRGD
comparators to accurately sense the output voltage. The
effect of the PWRGD lower threshold can be modified using
a resistor divider from the output to PWRLS to ground, as
shown in Figure 23.
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