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參數(shù)資料
| 型號： | NCP5214A |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 2−in−1 Notebook DDR Power Controller |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 376K |
| 代理商： | NCP5214A |
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NCP5214A
http://onsemi.com
16
VDDQ Regulator in Standby Mode (S3)
During state S3, a powersaving mode is activated when
the FPWM pin is pulled to VCCA. In powersaving mode,
the switching frequency is reduced with the VDDQ output
current and the lowside FET is turned off after the
detection of negative inductor current, so as to enhance the
efficiency of the VDDQ regulator at light loads. The
switching frequency can be reduced smoothly until it
reaches the minimum frequency at about 15 kHz.
Therefore, perceptible audible noise can be avoided at light
load condition.
In powersaving mode, the lowside MOSFET is turned
off after the detection of negative inductor current and the
converter cannot sink current. The powersaving mode can
be disabled by pulling the FPWM pin to ground. Then, the
converter operates in forcedPWM mode with fixed
switching frequency and ability to sink current.
Fault Protection of VDDQ Regulator
During state S0 and S3, external resistor (RL1) between
OCDDQ and VIN sets the overcurrent trip threshold for the
highside switch. An internal 31 A current sink (IOC) at
OCDDQ pin establishes a voltage drop across this resistor
and develops a voltage at the noninverting input of the
current limit comparator. The voltage at the noninverting
input is compared to the voltage at SWDDQ pin when the
highside gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than that at the
noninverting input for 4 consecutive internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
shorttoground condition on SWDDQ or VDDQ. The IC
will be reset once VCCA or VDDQEN is cycled.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figures 2 and 39.
VTT Active Terminator in Normal Mode (S0)
The VTT active terminator is a twoquadrant linear
regulator with two internal Nchannel power FETs. It is
capable of sinking and sourcing at least 1.5 A continuous
current and up to 2.4 A transient peak current. It is activated
in normal mode in state S0 when the VTTEN pin is HIGH
and VDDQ is in regulation. Its input power path is from
VDDQ with the internal FETs gate drive power derived
from VCCA. The VTT internal reference voltage is derived
from the DDQREF pin. The VTT output is set to VDDQ/2
when VTT output is connecting to the FBVTT pin directly.
This regulator is stable with only a minimum 20 F output
capacitor. The VTT regulator will have an internal
softstart when it is transited from disable to enable.
During the VTT softstart, a current limit is used as a
current source to charge up the VTT output capacitor. The
current limit is initially 1.0 A during VTT softstart. It is
then increased to 2.5 A after 128 internal clock cycles
which is typically 0.32 ms.
VTT Active Terminator in Standby Mode (S3)
VTT output is highimpedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional
current limit is implemented, preset at the minimum of
2.5 A magnitude.
Thermal Consideration of VTT Active Terminator
The VTT terminator is designed to handle large transient
output currents. If large currents are required for very long
duration, then care should be taken to ensure the maximum
junction temperature is not exceeded. The 5x6 DFN22 has
a thermal resistance of 35 C/W (dependent on air flow,
grade of copper, and number of vias).
In order to take full
advantage from this thermal capability of this package, the
thermal pad underneath must be soldered directly onto a
PCB metal substrate to allow good thermal contact. It is
recommended that PCB with 2 oz. copper foil is used and
there should have 6 to 8 vias with 0.6 mm hole size
underneath the package’s thermal pad connecting the top
layer metal to the bottom layer metal and the internal layer
metal substrates of the PCB.
VTTREF Output
The VTTREF output tracks VDDQREF/2 at
accuracy. It has source current capability of up to 15 mA.
VTTREF should be bypassed to analog ground of the
device by 1.0 F ceramic capacitor for stable operation.
The VTTREF is turned on as long as VDDQEN is pulled
high. In S0 mode, VTTREF softstarts with VDDQ and
tracks VDDQREF/2. In S3 mode, VTTREF is kept on with
VDDQ. VTTREF is turned off only in S4/S5 like VDDQ
output.
2%
Output Voltages Sensing
The VDDQ output voltage is sensed across the FBDDQ
and AGND pins. FBDDQ should be connected through a
feedback resistor divider to the VDDQ point of regulation
which is usually the local VDDQ bypass capacitor for load.
The AGND should be connected directly through a sense
trace to the remote ground sense point which is usually the
ground of local VDDQ bypass capacitor for load.
The VTT output voltage is sensed between the FBVTT
and VTTGND pins. The FBVTT should be connected to
the VTT regulation point, which is usually the VTT local
bypass capacitor, via a direct sense trace. The VTTGND
should be connected via a direct sense trace to the ground
of the VTT local bypass capacitor for load.
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