參數(shù)資料
型號： NCP5214A
廠商： ON SEMICONDUCTOR
英文描述： 2−in−1 Notebook DDR Power Controller
文件頁數(shù)： 15/31頁
文件大小： 376K
代理商： NCP5214A
NCP5214A
http://onsemi.com
15
DETAILED OPERATING DESCRIPTION
General
The NCP5214A
2in1 Notebook DDR Power
Controller combines the efficiency of a PWM controller for
the VDDQ supply, with the simplicity of using a linear
regulator for the VTT termination voltage power supply.
The VDDQ output can be adjusted through the external
potential divider, while the VTT is internally set to track
half VDDQ.
The inclusion of VDDQ power good voltage monitor,
softstart, VDDQ
overcurrent
overvoltage
and
undervoltage
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN22.
protection,
protections, supply
VDDQ
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever VDDQEN is high (exceed 1.4 V). An
internal bandgap voltage, VREF, is then generated. Once
VREF reaches its regulation voltage, an internal signal
VREFGD will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the VDDQ and VTT regulators in
accordance with Table 1. A timing diagram is shown in
Figure 38.
VDDQ Switching Regulator in Normal Mode (S0)
The VDDQ regulator is a switching synchronous
rectification buck controller directly driving two external
NChannel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz
15%. As can be observed from Figure 1, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at VDDQ = VFBDDQ
×
(1 + R1/R2). This amplifier compares the feedback voltage
with an internal VREF (= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulsewidthmodulated signal. This PWM signal drives
the external NChannel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor COUT1
filter the output waveform. The VDDQ output voltage
ramps up at a predefined softstart rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
VDDQ is detected, signal INREGDDQ will go HIGH to
notify the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive
nonoverlap
timing
complementary gate drive output signals is provided to
reduce large shootthrough current that degrades
efficiency.
control
of
the
Tolerance of VDDQ
The tolerance of VFBDDQ and the ratio of external
resistor divider R1/R2 both impact the precision of VDDQ.
With the control loop in regulation, VDDQ = VFBDDQ
×
(1 + R1/R2). With a worst case (for all valid operating
conditions) VFBDDQ tolerance of
range of
2.5% for VDDQ = 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500
1.5%, a worst case
1%.
Table 1. State, Operation, Input and Output Condition Table
Mode
Input Conditions
Operating Conditions
Output Conditions
VCCA
VOCDDQ
VDDQEN
VTTEN
FPWM
VDDQ
VTTREF
VTT
TGDDQ
BGDDQ
PGOOD
S5
Low
X
X
X
X
HZ
HZ
HZ
Low
Low
Low
S5
X
Low
X
X
X
HZ
HZ
HZ
Low
Low
Low
S0
High
High
High
High
X
Normal
Normal
Normal
Normal
Normal
HZ
S3
High
High
High
Low
High
Standby
Normal
HZ
Standby
(Power
saving)
Standby
(Power
saving)
HZ
S3
High
High
High
Low
Low
Normal
Normal
HZ
Normal
Normal
HZ
S5
X
X
Low
X
X
HZ
HZ
HZ
Low
Low
Low
相關(guān)PDF資料
PDF描述
NCP5214AMNR2G 2−in−1 Notebook DDR Power Controller
NCP5214 2-in-1 Notebook DDR Power Controller
NCP5214MNR2 2-in-1 Notebook DDR Power Controller
NCP5218 2−in−1 Notebook DDR Power Controller
NCP5218MNR2G 2−in−1 Notebook DDR Power Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NCP5214AMNR2G 功能描述:DC/DC 開關(guān)控制器 OSPI 2 IN 1 NTEBOOK RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5214EVB 功能描述:電源管理IC開發(fā)工具 ANA NCP5214 EVAL BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V
NCP5214MNR2 功能描述:DC/DC 開關(guān)控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5214MNR2G 功能描述:DC/DC 開關(guān)控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5215 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual Synchronous Buck Controller for Notebook Power System
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*