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參數(shù)資料
| 型號(hào)： | NCP4331 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Synchronous Buck Controller for High Efficiency Post Regulation |
| 中文描述： | 同步降壓控制器的高效率后調(diào)整 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 195K |
| 代理商： | NCP4331 |
NCP4331
http://onsemi.com
15
turn on the low-side MOSFET is significantly
minimized (no Miller plateau) and the switching
losses are very low.
2.
Low-side Turn Off (t1)
: The high-side MOSFET
turns on about 70 ns after the low-side opening.
During this 70 ns time when both switches are off,
the body diode of the low-side MOSFET derives
the coil current (in nominal load condition, when
the coil current is positive, i.e., when it flows
toward the output). As a result, the low-side
MOSFET turns off while its drain-source voltage
keeps around zero due to its body diode activation.
Again, the energy Qg to be extracted for opening
the low-side MOSFET is small and the switching
losses are low.
3.
High-side Turn Off (t4)
: The low-side MOSFET
turns on 70 ns before the high-side MOSFET
turns off. Hence, just before t4, the input voltage
being low and the low-side MOSFET being on,
the voltage across the high-side MOSFET is
nearly zero while the low-side MOSFET generally
already derives the major part of the coil current.
Finally, this transition is very soft (low current, no
voltage)
Only the high-side turn on (t2) that leads to switch the full
current and voltage, is “hard”. This sequencing that makes
soft 3 transitions over 4, helps maximize the efficiency of the
post-regulator.
Other Drive Constraints
The post-regulator is the seat of large “dV/dt” that may
disturb the system operation if the drivers are not strong
enough to contain them. There are two “dV/dt” the circuit
must face:
1. When the high-side MOSFET turns on, the
potential of the “HB” node sharply increases and
hence, it produces a huge current through the C
rss
capacitor of the low-side MOSFET. This current
may lead to a parasitic turn on of the low-side
MOSFET if the driver impedance is too high to
absorb this current without a significant increase
of the driver voltage. For instance, a 30 V / 10 ns
dV/dt produces a 450 mA current through a
150 pF C
rss
(450 = 150 pF
(30 V / 10 ns)). If the
driver voltage must keep below 2.5 V to prevent
unwanted turn on, the driver sink resistor should
be less than: R
sink
= (2.5 V/0.45 A) = 5.5 .
2. Similarly, the sink capability of the high-side
driver must be high enough to face the high dV/dt
that occurs when the post-regulator input voltage
abruptly turns high. Again, a 30 V / 10 ns dV/dt
would produce a 450 mA current through a 150 pF
C
rss
and the driver sink resistor should be less
than: R
sink
= 5.5 .
Finally, the immunity to (dV/dt)s is the main criterion in
the dimensioning of the driver sink capability. Both the low
and high side drivers that features a 4
resistance, allows a robust post-regulator operation.
It must be noted that the drivers remain in a sinking mode
whenever the circuit is off following an Undervoltage
Lockout condition, the activation of the thermal shutdown
or an undervoltage condition.
maximal sink
Synchronization Block
The “SYNC” pin is designed to receive the post-regulator
input voltage (“V
in
” of the application schematic). When
this voltage drops below the 2.5 V internal threshold, the
circuit generates a “RESET” pulse signal that is long enough
(about 250 ns) to:
Activate the internal switch that is implemented to
ground and fully discharge the C
RAMP
timing capacitor.
The circuit is then initialized for a next cycle.
Reset the PWM latch and hence, initiate a
free-wheeling phase (the circuit turns on the low-side
MOSFET and 70 ns later, it opens the high-side
MOSFET).
Figure 24. Synchronization Block
SYNC
RESET
SYNC
Q
RESET
Delay
Delay
-
+
S
R
Q
V
sync
H/
V
sync
L
+
V
DD
The synchronization block generates a short reset pulse. Its duration (“delay) is 250 ns typically.
The voltage that is applied to the “SYNC” pin, may be
slightly negative during one part of the period. The
NCP4331 incorporates a negative protection system that
clamps the negative spikes that may cause an improper
operation of the circuit. The protection is fully effective as
long as the pin 16 source current is kept below 2 mA.
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