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參數(shù)資料
| 型號(hào)： | NCN8024RDWR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD IC2 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | * |
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NCN8024R
http://onsemi.com
9
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C; FCLKIN = 10 MHz)
Symbol
Unit
Max
Typ
Min
Rating
|IIH|
|IIL|
CRD_PRES, CRD_PRES
High level input leakage current, VIH = VDD
CRD_PRES
Low level input leakage current, VIL = 0 V
CRD_PRES
3
10
1
10
mA
5
8
12
ms
ICRD_IO CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation
15
mA
ICRD_CLK CRD_CLK Current Limitation
70
mA
ICRD_RST CRD_RST Current Limitation
20
mA
tact
Activation Time (Note 7)
30
100
ms
tdeact
Deactivation Time (Note 7)
30
250
ms
Temp SD Shutdown Temperature
160
°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Guaranteed by design and characterization
POWER SUPPLY
The NCN8024R smart card interface has two power
supplies: VDD and VDDP.
VDD is usually common to the system controller and the
interface. The applied VDD ranges from 2.7 V up to 5.5 V.
If VDD goes below 2.30 V typical (UVLOVDD) a
powerdown sequence is automatically performed. In that
case the interrupt (INT) pin is set Low.
A Low DropOut (LDO) and low noise regulator is used
to provide the 3 V or 5 V power supply voltage (CRD_VCC)
to the card. VDDP is the LDO’s input voltage. CRD_VCC is
the LDO output. The typical distributed reservoir output
capacitor connected to CRD_VCC is 100 nF + 220 nF. To
minimize dI/dt effects the capacitor of 100 nF is connected
as close as possible to the CRD_VCC’s pin and the 220 nF
one as close as possible to the card connector C1 pin. Both
feature very low ESR values (lower than 50 m
W). The
decoupling capacitors on VDD and VDDP respectively
100 nF and 10
mF have also to be connected close to the
respective IC pins.
The CRD_VCC pin can source up to 70 mA continuously
over the VDDP range, the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
There’s no specific sequence for applying VDD or VDDP.
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the Power
On Reset (POR) circuitry and the under voltage lockout
(UVLO) detection (VDD voltage dropout detection).
PORADJ pin allows the user, according to the considered
application, to adjust the VDD UVLO threshold. If not used
PORADJ pin is connected to Ground (recommended even
if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no
further signal can be provided or supported during this
period.
The system is ready to operate when the input voltage has
reached the minimum VDD. Considering this, the
NCN8024R will detect an UnderVoltage situation when
the input supply voltage will drop below 2.30 V typical.
When VDD goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during poweron and poweroff of
the VDD supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
UVLO + R1 ) R2
R2
VPOR
If PORADJ is connected to Ground the VDD UVLO
threshold (VDD falling) is typically 2.30 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the VDD supply dropout detection
level which enables a deactivation sequence if the VDD
voltage is too low.
For example, there are microcontrollers for which the
minimum supply voltage insuring a correct operating is
higher than 2.70 V, increasing UVLOVDD (VDD falling) is
consequently necessary. Considering for instance a resistor
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