VCC = 0 V; V
參數(shù)資料
型號(hào)： NBSG53ABAEVB
廠商： ON Semiconductor
文件頁(yè)數(shù)： 18/18頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL BBG NBSG53ABA
產(chǎn)品變化通告： Product Discontinuation 21/Jun/2007
標(biāo)準(zhǔn)包裝： 1
其它名稱(chēng)： NBSG53ABAEVB-ND
NBSG53ABAEVBOS
NBSG53A
http://onsemi.com
9
Table 10. AC CHARACTERISTICS for FCBGA16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
70°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
DFF
(See Figures 5, 7, 9, 10, and 11)
(Note 26)
DIV/2
8
10
8
10
8
10
GHz
tPLH,
tPHL
Propagation Delay to Output Differential
CLK→Q, Q
(OLS = VCC)
(OLS = VCC 0.4 V)
(OLS = VCC 0.8 V, OLS = FLOAT)
**(OLS = VEE)
160
150
155
210
200
205
260
250
255
160
155
160
215
205
210
270
255
260
165
160
220
210
215
275
260
270
ps
SEL→Q, Q
(OLS = VCC)
(OLS = VCC 0.4 V)
(OLS = VCC 0.8 V, OLS = FLOAT)
**(OLS = VEE)
165
160
220
210
215
210
275
260
270
260
170
160
165
160
225
210
220
215
280
260
275
270
170
160
165
225
210
220
280
260
275
R→Q, Q
(OLS = VCC) DIV/2
(OLS = VCC) DFF
(OLS = VCC 0.4 V) DIV/2
(OLS = VCC 0.4 V) DFF
(OLS = VCC 0.8 V, OLS = FLOAT) DIV/2
(OLS = VCC 0.8 V, OLS = FLOAT) DFF
**(OLS = VEE) DIV/2
**(OLS = VEE) DFF
220
200
215
195
220
200
215
195
295
270
285
260
290
265
285
260
370
340
355
325
360
330
355
325
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
tSKEW
Duty Cycle Skew (Notes 27 and 29) DFF
5
20
5
20
5
20
ps
tJITTER
RMS Random Clock Jitter
fin v 8 GHz
(See Figures 4 and 6) (Note 26)
PeaktoPeak Data Dependent Jitter
fin = 8 Gb/s
0.5
1.5
0.5
TBD
1.5
0.5
1.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% 80%)
@ 1 GHz
Q, Q
(OLS = VCC)
(OLS = VCC 0.4 V)
(OLS = VCC 0.8 V, OLS = FLOAT)
**(OLS = VEE)
30
20
25
50
40
45
65
60
65
30
20
25
50
40
45
65
60
65
30
20
25
50
40
45
65
60
65
ps
ts
Setup Time
D→CLK
30
14
30
10
30
13
ps
th
Hold Time
D→CLK
25
12
25
7
25
9
ps
trr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to
VCC 2.0 V. Input edge rates is 40 ps (20% 80%).
27.See Figure 14. tSKEW = |tPLH tPHL| for a nominal 50% differential clock input waveform.
28.VINPP (MAX) cannot exceed VCC VEE (Applicable only when VCC VEE < 2600 mV).
29.See Figure 10. Duty Cycle % vs. Frequency.
**When an output level of 400 mV is desired and VCC VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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