鍨嬭櫉(h脿o)锛� | NBSG16VSMNHTBG |
寤犲晢锛� | ON Semiconductor |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 12/14闋�(y猫) |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC RCVR/DVR SIGE DIFF 16QFN |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
椤炲瀷锛� | 鏀剁櫦(f膩)鍣� |
鎳�(y墨ng)鐢細 | 鍎€琛� |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
灏佽/澶栨锛� | 16-VFQFN 瑁搁湶鐒婄洡 |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-QFN锛�3x3锛� |
鍖呰锛� | 甯跺嵎 (TR) |
閰嶇敤锛� | NBSG16VSBAEVBOS-ND - BOARD EVAL BBG NBSG16VSBA |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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NBSG16MNHTBG | IC RCVR/DRVR RSECL SIGE DF 16QFN |
NBSG16VSMNR2G | IC RCVR/DRIVER SIGE DIFF 16QFN |
LFXP20C-4F388C | IC FPGA 19.7KLUTS 268I/O 388-BGA |
LFXP20C-3F388I | IC FPGA 19.7KLUTS 268I/O 388-BGA |
LFXP20E-4FN388C | IC FPGA 19.7KLUTS 388FPBGA |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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NBSG16VSMNR2 | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕�(d貌ng)鍣� 2.5V/3.3V SiGe Diff RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
NBSG16VSMNR2G | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕�(d貌ng)鍣� 2.5V/3.3V SiGe Diff w/Variable Output RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
NBSG53A | 鍒堕€犲晢:ONSEMI 鍒堕€犲晢鍏ㄧū:ON Semiconductor 鍔熻兘鎻忚堪:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS |
NBSG53A/D | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS |
NBSG53A_06 | 鍒堕€犲晢:ONSEMI 鍒堕€犲晢鍏ㄧū:ON Semiconductor 鍔熻兘鎻忚堪:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS |