參數資料
| 型號： | NB7L32MMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 6/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIVIDER 1:2 16-QFN |
| 標準包裝： | 3,000 |
| 類型： | 時鐘除法器 |
| PLL： | 無 |
| 輸入： | CML，ECL，LVDS，LVPECL |
| 輸出： | CML |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 14GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB7L32M
http://onsemi.com
5
Symbol
Characteristic
40°C
255C
855C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@ VINPP(MIN))
fin ≤ 7 GHz
fin ≤ 12 GHz
190
160
330
320
190
160
330
320
190
160
330
320
mV
fIN
Maximum Input Clock Frequency
(See Figure 2)
12
14
12
14
12
14
GHz
tPLH,
tPHL
Propagation Delay to
CLK to Q
Output Differential (See Figure 7)
R to Q
130
200
155
240
200
300
130
200
155
240
200
300
130
200
155
260
200
300
ps
tskew
Duty Cycle Skew (Note 9)
DevicetoDevice Skew (Note 12)
2
6
20
50
2
6
20
50
2
6
20
50
tRR
Reset Recovery (See Figure 7)
300
135
300
135
300
135
ps
tPW
Minimum Pulse Width
R 500
210
500
210
500
210
ps
tJITTER
Random Clock Jitter (RMS)
fin ≤ 7 GHz
(Note 11)
fin = 12 GHz
0.13
0.14
0.5
0.13
0.14
0.5
0.13
0.14
0.5
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
150
2500
150
2500
150
2500
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
(20% 80%)
30
45
30
45
30
45
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ 1 GHz.
10.VINPP(MAX) cannot exceed VCC VEE. Input voltage swing is a singleended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12.Devicetodevice skew is measured between outputs under identical transition @ 1 GHz.
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fOUT) at
Ambient Temperature (VINPP = 150 mV)
INPUT CLOCK FREQUENCY (GHz)
0
50
100
150
200
250
300
350
400
450
2
4
6
8
10
12
14
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
VCC = 3.3 V
VCC = 2.5 V
0
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