參數(shù)資料
型號: NB6L11D
廠商: ON SEMICONDUCTOR
元件分類: 時鐘及定時
英文描述: 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
中文描述: 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: SOIC-8
文件頁數(shù): 7/12頁
文件大?。?/td> 114K
代理商: NB6L11D
NB6L11
http://onsemi.com
7
Table 7. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
= 3.465 V to 2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V (Note 17)
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
OUTPP
Output Voltage Amplitude
(See Figures 2 & 3
)
f
in
f
in
3 GHz
6 GHz
480
270
700
300
480
270
700
300
480
270
700
300
mV
t
PLH
,
t
PHL
Propagation Delay to
Output Differential @ 1 GHz
D to Q, Q
110
150
190
110
150
200
120
160
220
ps
t
SKEW
Duty Cycle Skew
Within Device Skew
DevicetoDevice Skew
(Note 18)
2
5
15
10
15
60
2
5
15
10
15
60
2
5
15
10
15
60
ps
t
JITTER
RMS Random Clock Jitter
(Note 19)
PeaktoPeak Data Dependent Jitter
(Note 20)
f
in
6 GHz
f
in
6 Gb/s
0.2
2
1
12
0.2
2
1
12
0.2
2
1
12
ps
V
INPP
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 21)
75
700
2500
75
700
2500
75
700
2500
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% 80%)
Q, Q
30
75
120
30
75
120
30
75
120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
17.Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 to V
2.0 V. Input edge rates 40 ps (20% 80%).
18.See Figure 9 t
= |t
t
| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
transitions and conditions @ 1 GHz.
19.Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
20.Additive PeaktoPeak data dependent jitter with NRZ PRBS 2
23
1 data rate at 6 Gb/s.
21.V
INPP(max)
cannot exceed V
CC
V
EE
(applicable only when V
CC
V
EE
< 2500 mV). Input voltage swing is a singleended measurement
operating in differential mode
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
4
5
6
7
8
3
O
Figure 2. Output Voltage Amplitude (V
OUTPP
)
versus Input Clock Frequency (f
IN
) and
Temperature at V
CC
V
EE
= 3.3 V
INPUT CLOCK FREQUENCY (GHz)
85
°
C
40
°
C
25
°
C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
5
6
7
8
O
40
°
C
85
°
C
25
°
C
Figure 3. Output Voltage Amplitude (V
OUTPP
)
versus Input Clock Frequency (f
IN
) and
Temperature at V
CC
V
EE
= 2.5 V
INPUT CLOCK FREQUENCY (GHz)
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