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參數(shù)資料
| 型號(hào)： | NB3RL02FCT2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:2 52MHZ 8-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 輸入： | 時(shí)鐘 |
| 輸出： | LVCMOS |
| 頻率 - 最大： | 52MHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 8-WLCSP（1.57x.77） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NB3RL02FCT2GOSDKR |
NB3RL02
http://onsemi.com
6
APPLICATION INFORMATION
Typical Application
A typical mobile application for the NB3RL02 is shown
in Figure 2. An external low noise TCXO clock source is
powered by the NB3RL02’s 1.8 V regulated LDO and is
buffered to drive a mobile GPS receiver and WLAN
transceiver. Each peripheral can independently request an
active clock by asserting a clock request line (CLK_REQ1
or CLK_REQ2).
Figure 2. Mobile Application
When both clock request lines are logic LOW, the
NB3RL02 enters a current-saving shutdown mode. In this
mode, the LDO output goes to 0 V and turns off the TCXO.
Also, the unpowered CLK_OUT1 and CLK_OUT2 outputs
are pulled to GND.
When the NB3RL02 receives a HIGH from either
peripheral CLK_REQn, the 1.8 V LDO output is enabled
and will power the TCXO. The output of the TCXO can be
a square wave, sine wave, or clipped sine wave and is
converted to a buffered square wave.
Input Clock to Output Square Wave Generator
Figure 3 shows the MCLK_IN input having an internal
AC coupling capacitor. This allows either a square or sine
wave signal to be directly connected from a TCXO.
Therefore, an external series capacitor is not required.
MCLK _IN
CMCLK
Figure 3. Input Stage
The clock frequency band of the NB3RL02 is 10 MHz to
52 MHz with all performance metrics specified at 26 MHz.
Typical input sinusoidal signal amplitude is 0.8 VPP for
specified performance, but amplitudes as low as 0.3 VPP are
acceptable, but with reduced phase noise and jitter
performance.
CLK_OUT1 and CLK_OUT2 Outputs
The CLK_OUT1 and CLK_OUT2 outputs drive 1.8 V
LVCMOS levels with rise/fall times within 1 ns to 5 ns with
load capacitors between 10 pF and 50 pF. These relatively
slow edge rates will minimize EMI radiation into the system.
When not requested, each output is set to Low to avoid false
clocking of the load device.
LDO
The integrated low noise 1.8 V LDO provides power
internal to the NB3RL02 as well as a power source for an
external clock such as a TCX0. The input range of the LDO
allows the device to be powered directly from a single cell
Li battery. The LDO is enabled when either of the
CLK_REQn signals is High.
When disabled, the device turns off the LDO and enters a
low power shutdown mode consuming less than 1
mA from
the battery.
The LDO requires an output decoupling capacitor in the
range of 1
mF to 10 mF for compensation and high frequency
PSR. An input bypass capacitor of 1
mF or larger is
recommended.
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