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參數(shù)資料
| 型號(hào)： | NB3N853531EDTR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FANOUT BUFFER LVPECL 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 頻率 - 最大： | 266MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
NB3N853531E
http://onsemi.com
3
Figure 3. CLK_EN Timing Diagram
CLK
CLK_EN
Enabled
Disabled
Q[0:3]
Table 3. ATTRIBUTES (Note 2)
Characteristics
Value
Internal Input Pullup Resistor
50 kW
Internal Input Pulldown Resistor
50 kW
Cin Input Capacitance
4 pF
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Level 1
Flammability Rating
Oxygen Index
UL 94 V0 @ 0.125 in
28 to 34
Transistor Count
333 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Supply Voltage
4.6
V
Vin
Input Voltage
0.5 v VI v VCC + 0.5
V
Iout
Output Current
Continuous
Surge
50
100
mA
TA
Operating Temperature Range, Industrial
40 to v +85
°C
Tstg
Storage Temperature Range
65 to +150
°C
θJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
SingleLayer
PCB (700 mm2,
2 oz)
128
°C/W
200 lfpm
MultiLayer
PCB (700 mm2,
2 oz)
94
θJC
Thermal Resistance (JunctiontoCase)
(Note 4)
TSSOP20
23 to 41
°C/W
Tsol
Wave Solder
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power).
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