參數(shù)資料
型號: NB3N206SDG
廠商: ON Semiconductor
文件頁數(shù): 7/19頁
文件大?。?/td> 0K
描述: IC CLK DVR RECEIVER M-LVDS 8SOIC
標(biāo)準(zhǔn)包裝: 98
類型: 緩沖器/驅(qū)動器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
輸入: LVCMOS,LVDS
輸出: LVCMOS,LVDS
頻率 - 最大: 200MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
NB3N201S, NB3N206S
http://onsemi.com
15
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
LIVE INSERTION/GLITCHFREE POWER UP/DOWN
The NB3N201/206 family of products provides a
glitchfree power up/down feature that prevents the
MLVDS outputs of the device from turning on during a
power up or power down event. This is especially important
in live insertion applications, when a device is physically
connected to an MLVDS multipoint bus and VCC is
ramping.
While the MLVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
Figure 17 shows the performance of the receiver output pin,
R (CHANNEL 2), as VCC (CHANNEL 1) is ramped. The
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
operation until VCC has reached a steady state value.
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