Table 4. DC CHARACTERISTICS (VCC = " />
參數(shù)資料
型號(hào): NB3N108KMNR4G
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/9頁(yè)
文件大小: 0K
描述: IC FANOUT BUFFER 1:8 HCSL 32QFN
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 是/是
輸入: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
輸出: HCSL,LVDS
頻率 - 最大: 400MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
NB3N108K
http://onsemi.com
4
Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = 40°C to +85°C Note 4)
Symbol
Characteristic
Min
Typ
Max
Unit
IGND
GND Supply Current (All Outputs Loaded)
60
90
mA
ICC
Power Supply Current (All Outputs Loaded)
190
230
mA
IIH
Input HIGH Current
2.0
150
mA
IIL
Input LOW Current
150
2.0
mA
RTIN
Internal Input Termination Resistor
45
50
55
W
DIFFERENTIAL INPUT DRIVEN SINGLEENDED
Vth
Input Threshold Reference Voltage Range (Note 5)
350
VCC 1000
mV
VIH
Single*Ended Input HIGH Voltage
Vth + 150
VCC
mV
VIL
Single*Ended Input LOW Voltage
GND
Vth 150
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9)
VIHD
Differential Input HIGH Voltage
425
VCC 850
mV
VILD
Differential Input LOW Voltage
GND
VCC 1000
mV
VID
Differential Input Voltage (VIHD * VILD)
150
VCC 850
mV
VCMR
Input Common Mode Range
350
VCC 1000
mV
HCSL OUTPUTS (Figure 4)
VOH
Output HIGH Voltage
600
740
900
mV
VOL
Output LOW Voltage
150
0
150
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurements taken with with outputs loaded 50 W to GND, see Figure 6. Connect a 475 W resistor from IREF (Pin 1) to GND per Figure 6.
5. Vth is applied to the complementary input when operating in single ended mode per Figure 4.
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