Figure 2. Pinout Configuration (Top View) 1 XTAL_OUT 16 XTAL_IN/CLK 2 EN" />
參數(shù)資料
型號(hào)： NB3H83905CDTR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 7/14頁(yè)
文件大?。?/td> 0K
描述： IC CLK BUFFER 1:6 100MHZ 16TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 扇出緩沖器（分配）
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 無(wú)/無(wú)
輸入： LVCMOS，LVTTL，晶體
輸出： LVCMOS，LVTTL
頻率 - 最大： 100MHz
電源電壓： 1.6 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
NB3H83905C
http://onsemi.com
2
Figure 2. Pinout Configuration (Top View)
1
XTAL_OUT
16 XTAL_IN/CLK
2
ENABLE2
3
GND
4
BCLK0
15 ENABLE1
14 BCLK5
13 VDDO
SOIC16/TSSOP16
5
12
6
7
8
11
10
9
VDDO
BCLK4
BCLK1
GND
BCLK2
GND
BCLK3
VDD
BCLK5
VDDO
BCLK4
GND
BCLK0
VDDO
BCLK1
ENABLE2
XT
AL_OUT
XT
AL_IN/CLK
ENABLE1 NC
GND
BCLK2
V
DD
BCLK3
QFN20
1
2
3
4
5
15
14
13
12
11
10
9
8
7
6
16
17
18
19
20
EP
Exposed Pad
Table 1. PIN DESCRIPTION
SOIC16 /
TSSOP16
QFN20
Name
I/O
Description
1
19
XTAL_OUT
Crystal Interface
Oscillator Output to drive Crystal
2
20
ENABLE 2
LVTTL /
LVCMOS Input
Synchronous Enable Input for BCLK5 Output. Switches only when
HIGH. Open default condition HIGH due to an internal pullup resistor
to VCC.
3, 7, 11
1, 2, 6, 7,
11, 12
GND
GND Supply pins. All GND, VDD and VDDO pins must be externally
connected to power supply to guarantee proper operation.
4, 6, 8,
10, 12, 14
3, 5, 8,
10, 13, 15
BCLK0, 1,
2, 3, 4, 5
LVCMOS
Outputs
Buffered Clock Outputs
5, 13
4, 14
VDDO
POWER
Positive Supply voltage for outputs. All GND, VDD and VDDO pins
must be externally connected to power supply to guarantee proper
operation. Bypass with 0.01 mF cap to GND.
9
VDD
POWER
Positive Supply voltage for core. All GND, VDD and VDDO pins must
be externally connected to power supply to guarantee proper
operation. Bypass with 0.01 mF cap to GND.
16
NC
No Connect
15
17
ENABLE 1
LVTTL /
LVCMOS Input
Synchronous Enable Input for BCLK0/1/2/3/4 Output block. Switches
only when HIGH. Open default condition HIGH due to an internal
pullup resistor to VCC
16
18
XTAL_IN/
CLK
Crystal Interface
Oscillator Input from Crystal. Single ended Clock Input.
EP
The Exposed Pad (EP) on the QFN20 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heatsinking conduit. The pad is
not electrically connected to the die, but is recommended to be
electrically and thermally connected to GND on the PC board.
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