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參數(shù)資料
型號(hào)： NB3H83905CDTR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 12/14頁(yè)
文件大?。?/td> 0K
描述： IC CLK BUFFER 1:6 100MHZ 16TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 扇出緩沖器（分配）
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 無(wú)/無(wú)
輸入： LVCMOS，LVTTL，晶體
輸出： LVCMOS，LVTTL
頻率 - 最大： 100MHz
電源電壓： 1.6 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
NB3H83905C
http://onsemi.com
7
Table 7. AC CHARACTERISTICS
Symbol
Characteristic
Min
Typ
Max
Unit
VDD = VDDO = 3.135 V to 3.465 V (3.3 V $ 5%); GND = 0 V, TA = 405C to +855C (Note 5)
Fmax
Input Frequency Crystal
3
40
MHz
Input Frequency Clock (XTAL_IN/CLK)
DC
100
tEN / tDIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn
4
Cycles
tSKEWDC
Duty Cycle Skew (See Figure 4)
48
52
%
tSKEWOO
Output to Output Skew Within A Device (same conditions)
0
50
80
ps
FNOISE
PhaseNoise Performance fout = 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
123
142
153
164
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.08
ps
tr/tf
Output rise and fall times (20%; 80%)
200
800
ps
VDD = VDDO = 2.375 V to 2.625 V (2.5 V $ 5%); GND = 0 V, TA = 405C to +855C (Note 5)
Fmax
Input Frequency Crystal
3
40
MHz
Input Frequency Clock (XTAL1)
DC
100
tEN / tDIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn
4
Cycles
tSKEWDC
Duty Cycle Skew (See Figure 4)
47
53
%
tSKEWOO
Output to Output Skew Within A Device (same conditions)
0
50
80
ps
FNOISE
PhaseNoise Performance fout = 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
118
137
151
165
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.13
ps
tr/tf
Output rise and fall times (20%; 80%)
200
800
ps
VDD = VDDO = 1.6 V to 2.0 V (1.8 V $ 0.2 V); GND = 0 V, TA = 405C to +855C (Note 5)
Fmax
Input Frequency Crystal
3
40
MHz
Input Frequency Clock (XTAL1)
DC
100
tEN / tDIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn
4
Cycles
tSKEWDC
Duty Cycle Skew (See Figure 4)
47
53
%
tSKEWOO
Output to Output Skew Within A Device (same conditions)
0
50
80
ps
FNOISE
PhaseNoise Performance fout = 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
129
145
147
157
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.27
ps
tr/tf
Output rise and fall times (20%; 80%)
200
900
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Crystal inputs v Fmax. Outputs loaded with 50 W to VDDO/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle.
See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading.
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