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參數(shù)資料
| 型號(hào)： | NB3F8L3010CMNG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FANOUT BUFFER 3:10 32QFN |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類(lèi)型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:10 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 輸入： | HCSL, LVDS, LVPECL, SSTL, 晶體 |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 管件 |
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NB3F8L3010C
http://onsemi.com
12
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the
package and the electrical performance, a land pattern must
be incorporated on the Printed Circuit Board (PCB) within
the footprint of the package corresponding to the exposed
metal pad or exposed heat slug on the package, as shown in
Figure 14. The solderable area on the PCB, as defined by the
solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should
be designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to
avoid any shorts. While the land pattern on the PCB provides
a means of heat transfer and electrical grounding from the
package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) is application specific
and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and
electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias
is incorporated in the land pattern. It is recommended to use
as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13 mils
(0.30 to 0.33 mm) with 1 oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during
the soldering process which may result in voids in solder
between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only.
Figure 14. Suggested Assembly for Exposed Pad Thermal Release Path – Cutaway View (not to scale)
ORDERING INFORMATION
Device
Package
Shipping
NB3F8L3010CMNG
QFN32
(PbFree)
74 Units / Rail
NB3F8L3010CMNR4G
QFN32
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB3F8L3010CMNR4G | 功能描述:時(shí)鐘緩沖器 1:10 LVCMOS FANOUT BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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| NB3H10-6PN | 制造商:ITT Interconnect Solutions 功能描述:PV3H10B6PN16 - Bulk |
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| NB3H12-10PN | 制造商:ITT Interconnect Solutions 功能描述:PV3H12B10PN15 - Bulk |
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