- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄189003 > NAND512W3B3BZA6E (NUMONYX) 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 PDF資料下載
參數(shù)資料
| 型號： | NAND512W3B3BZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 31/59頁 |
| 文件大?。?/td> | 998K |
| 代理商： | NAND512W3B3BZA6E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
37/59
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Figure 23. Garbage Collection
Garbage Collection
When a data page needs to be modified, it is faster
to write to the first available page, and the previous
page is marked as invalid. After several updates it
is necessary to remove invalid pages to free some
memory space.
To free this memory space and allow further pro-
gram operations it is recommended to implement
a Garbage Collection algorithm. In a Garbage Col-
lection software the valid pages are copied into a
free area and the block containing the invalid pag-
es is erased (see Figure 23.).
Wear-leveling Algorithm
For write-intensive applications, it is recommend-
ed to implement a Wear-leveling Algorithm to
monitor and spread the number of write cycles per
block.
In memories that do not use a Wear-Leveling Al-
gorithm not all blocks get used at the same rate.
Blocks with long-lived data do not endure as many
write cycles as the blocks with frequently-changed
data.
The Wear-leveling Algorithm ensures that equal
use is made of all the available write cycles for
each block. There are two wear-leveling levels:
■
First Level Wear-leveling, new data is
programmed to the free blocks that have had
the fewest write cycles
■
Second Level Wear-leveling, long-lived data is
copied to another block so that the original
block can be used for more frequently-
changed data.
The Second Level Wear-leveling is triggered when
the difference between the maximum and the min-
imum number of write cycles per block reaches a
specific threshold.
Error Correction Code
An Error Correction Code (ECC) can be imple-
mented in the Nand Flash memories to identify
and correct errors in the data.
For every 2048 bits in the device it is recommend-
ed to implement 22 bits of ECC (16 bits for line par-
ity plus 6 bits for column parity).
An ECC model is available in VHDL or Verilog.
Contact the nearest ST Microelectronics sales of-
fice for more details.
Figure 24. Error Detection
Valid
Page
Invalid
Page
Free
Page
(Erased)
Old Area
AI07599B
New Area (After GC)
New ECC generated
during read
XOR previous ECC
with new ECC
All results
= zero?
22 bit data = 0
YES
11 bit data = 1
NO
1 bit data = 1
Correctable
Error
ECC Error
No Error
ai08332
>1 bit
= zero?
YES
NO
相關PDF資料 |
PDF描述 |
|---|---|
| NAND512W3B3AN1 | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3BN1F | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND04GR4B3AN1 | 256M X 16 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND02GW3B3BZB1F | 256M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND02GW3B3BN1F | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NAND512W4A0AN6E | 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| NAND512W4A0AZA6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays |
| NAND64GAH0HZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND64GW3FGAZN6F | 制造商:Micron Technology Inc 功能描述:FULL CUSTOM MCP - Tape and Reel |
| NAND98R3M0CZBB5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。