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______________ Detailed Desc ription
Main Func tions
The MXD1210 executes five main functions to perform
reliable RAM operation and battery backup (see
Typical Operating Circuitand Figure 1):
1. RAM Power-Supply Switch: The switch directs
power to the RAM from the incoming supply or
from the selected battery, whichever is at the
greater voltage. The switch control uses the same
criterion to direct power to MXD1210 internal
circuitry.
2. Power-Failure Detection: The write-protection func-
tion is enabled when a power failure is detected.
The power-failure detection range depends on the
state of the TOL pin as follows:
Power-failure detection is independent of the battery-
backup function and precedes it sequentially as the
power-supply voltage drops during a typical power
failure.
3. Write Protection: This holds the chip-enable output
(
CEO
) to within 0.2V of V
CCI
or of the selected bat-
tery, whichever is greater. If the chip-enable input
(
CE
)is low (active) when power failure is detected,
then
CEO
is held low until
CE
is brought high, at
which time
CEO
is gated high for the duration of
the power failure. The preceding sequence com-
pletes the current RD/WR cycle, preventing data
corruption if the RAM access is a WR cycle.
4. Battery Redundancy: A second battery is optional.
When two batteries are connected, the stronger
battery is selected to provide RAM backup and to
power the MXD1210. The battery-selection circuitry
remains active while in the battery-backup mode,
selecting the stronger battery and isolating the
weaker one. The battery-selection activity is trans-
parent to the user and the system. If only one bat-
tery is connected, the second battery input should
be grounded.
5. Battery-Status Warning: This notifies the system
when the stronger of the two batteries measures
≤
2.0V. Each time the MXD1210 is repowered
(V
CCI
> V
CCTP
) after detecting a power failure, the
battery voltage is measured. If the battery in use is
low, following the MXD1210 recovery period, the
device issues a warning to the system by inhibit-
ing the second memory cycle. The sequence is as
follows:
First access: read memory location n, loc(n) = x
Second access: write memory location n,
loc (n) = complement (x)
Third access: read memory location n, loc (n) =
If the third access (read) is complement (x), then the
battery is good; otherwise, the battery is not good.
Return to loc(n) = x following the test sequence.
Freshness-S eal Mode
The freshness-seal mode relates to battery longevity
during storage rather than directly to battery backup.
This mode is activated when the first battery is connect-
ed, and is defeated when the voltage at V
CCI
first
exceeds V
CCTP
. In the freshness-seal mode, both bat-
teries are isolated from the system; that is, no current is
drained from either battery, and the RAM is not pow-
ered by either battery. This means that batteries can be
installed and the system can be held in inventory with-
out battery discharge. The positive edge rate at
VBATT1 and VBATT2 should exceed 0.1V/
μ
s. The bat-
teries will maintain their full shelf-life while installed in
the system.
Battery Bac kup
The Typical Operating Circuitshows the MXD1210 con-
nected in order to write protect the RAM when V
CC
is
less than 4.75V, and to provide battery backup to the
supply.
M
Nonvolatile RAM Controller
_______________________________________________________________________________________
5
CONDITION
V
CCTP
RANGE (V)
TOL = GND
4.75 to 4.50
TOL = V
CCO
4.50 to 4.25