參數(shù)資料
型號: MX881R
廠商: IXYS CORP
元件分類: 顯示驅(qū)動器
中文描述: LED DISPLAY DRIVER, PDSO16
封裝: 3 X 5 MM, DFN-16
文件頁數(shù): 13/13頁
文件大?。?/td> 398K
代理商: MX881R
MX881
IXYS
To write to the MX881 register, the master device will first issue a Start Bit. It will then transmit a 7-bit
address. In the MX881, the address is internally set to 0111111b. If the address in the message
corresponds to the address of the MX881, the device will issue an acknowledge. The master will send 8
bits of data. These 8 bits will be written into the control register. Another Acknowledge will follow. The
write sequence is illustrated in Figure 2.
To read the control register the master issues a read command by setting the R/Wn bit. The master will
then tri-state the data bus while the MX881 outputs data. See the example in Figure 2.
3-Wire SPI (Serial Peripheral Interface)
A standard 3-wire bi-directional serial interface is available (Figure 3). The interface signals are the serial
clock: SCLK, the serial data line: SDATA, and the serial chip enable: SCEn. SDATA is bidirectional.
In write mode, the microcontroller is writing to the MX881 control register. Each packet sent contains an
8-bit command followed by 8 bits of data to be written into the register.
When SCEn goes low, the rising edge of SCLK clocks in 8 bits, MSB first. At the end of the first
transmission byte, the MX881 determines whether the first byte is a recognized command. The MX881
only recognizes one write command “00011110”. If the command is recognized, the next byte clocked
into the MX881 will be written into the control register. This sequence is illustrated in Figure 3.
In read mode, a command is received which tells the MX881 to output the control register contents. The
MX881 only recognizes one read command: “01011110”. If the correct command is recognized, the
MX881 will output 8 bits of data beginning on the first falling edge of SCLK after the rising edge of SCLK
in which the last transmission bit was clocked in. In this manner, the first control register bit will be
available to the microcontroller on the next rising edge of SCLK. SCEn must remain low while the
MX881 is outputting data, going high after the MX881 has output the last bit. While the device is
outputting data, the microcontroller must stop driving the SDATA line so that the MX881 can drive the
data onto this bus. This sequence is also illustrated in Figure 3.
Table 4 - Serial Interface Timing
Symbol
Parameter
Condition
Min
Max
Units
TCYCS
Cycle Time
250
nS
THI, TLO
Pulse Width
50
nS
TDS
Data Setup Time
50
nS
TDH
Data Hold Time
30
nS
TSS
SCEn Setup Time, Write
30
nS
TSH
SCEn Hold Time, Write
30
nS
TACCS
Read Access Time
CL = 100pF
30
nS
TOHS
Read Output Disable Time
CL = 100pF
30
nS
TI2C_CS
I
2C Clock High to Start Bit
50
nS
TI2C_SC
I
2C Start Bit to Clock Low
50
nS
TI2C_DS
I
2C Data Valid to Clock High
50
nS
TI2C_DH
I
2C Clock Low to Data Change
30
nS
TI2C_CP
I
2C Clock High to Stop Bit
50
nS
TI2C_PC
I
2C Stop Bit to Clock Low
50
nS
MX881
9
7/30/07
Drawing No. 088109
www.claremicronix.com
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