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參數(shù)資料
| 型號(hào)： | MX812J |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動(dòng)時(shí)效編解碼器DRAM的控制 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 115K |
| 代理商： | MX812J |
VSR CODEC with DRAM CONTROL
6
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
The Controlling System: C-BUS Hardware Interface
C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a
μ
Controller and MX-COM's
New Generation integrated circuits. C-BUS is designed for a low IC pin-count, flexibility in handling variable amounts of data,
and simplicity of system design and
μ
Controller software.
It may be used with any
μ
Controller, and can, if desired, take advantage of the hardware serial I/O functions built into many
types of
μ
Controller. Because of this flexibility and because the BUS data-rate is determined solely by the
μ
Controller, the
system designer can choose a
μ
Controller appropriate to the overall system processing requirements.
Control of the functions and levels within the MX812 VSR Codec is by a group of Address/Commands and appended data
instructions from the system
μ
Controller to set/adjust the functions and elements of the MX812. The use of these instructions
Command
Assignment
Address/Command (A/C) Byte
Hex.
MSB
01
0
0
60
0
1
61
0
1
62
0
1
63
0
1
+
Data
Byte/s
Binary
LSB
1
0
1
0
1
General Reset
Write to Mode Register
Read Status Register
Store/Play Page
Wait
Table 1 – C-BUS Address/Commands
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
+
+
+
1 byte Instruction to Mode Register
1 byte Reply from Status Register
2 bytes Command
“Write to Mode Register”
– A/C 60
H
, followed by 1 byte of Command Data.
Interrupts
The MX812's Interrupt Output is driven by the Status Bit 7 (IF)
when the Mode Register Bit7 (IE) is set to a “1.”
The IF bit and the Interrupt Output (If enabled) are set when
the Store/Play/Wait command Buffer is emptied (MT bit) by
transferring from the buffer to the DRAM control circuits.
and/or
The IF bit and the Interrupt Output (if enabled) are set when
a Store, Play or Wait command has finished
and
the Command
Buffer is empty.
The notes below illustrate the IRQ pin conditions:
IF Bit
IE Bit
“0” cleared
“0” disable
“0” cleared
“1” enable
“1” Interrupt
“0” disable
“1” Interrupt
“1” enable
IRQ
High Z
High Z
High Z
V
SS
(logic “0”)
“General Reset”
– A/C 01
Upon Power-Up the “bits” in the MX812 registers will be
random (either “0” or “1”). A General Reset Command (01
)
will be required to “reset” all microcircuits on the C-BUS, and
has the following effect upon the MX812.
Clear all Mode Register bits to “0”
Status Register Bit 7 (IF) to “0”
Bits 5 and 6 (MT and I) to “1”
Halt any current Store, Play or Wait execution
Clear the Store/Play/Wait Command Buffer
Interrupt Output – IE
Controls the MX812 IRQ output driver.
Sampling Rates – SR
The CVSD Codec sampling rates. Accurate rates depend
upon the applied Xtal/clock frequency (see Table 5).
Memory Size – MS
The MX812 can operate with 1 x 1Mbit, 2 x 1Mbit or
1 x 4Mbit of DRAM (see Figure 4).
Powersave – PS
Powersaves the CVSD Codec only. Logic functions and
DRAM refresh are maintained.
Decode/Encode – DE
The Codec and DRAM operational mode.“
“Play” or “Store”
Mode Bits
Transmitted to 812 First
Interrupt Output
Enable
Disable
Sampling Rate
63kb/s
32kb/s
Memory (DRAM) Size
Single 4Mbit
1 or 2 x 1Mbit
Powersave
CVSD Codec Powersaved
CVSD Codec Powered
Decode/Encode
Decode – Play Mode
Encode – Store Mode
Not Used
Set to ‘zeros’
Setting
MSB
7
1
0
6
1
0
5
1
0
4
1
0
3
1
0
2
0
1
0
0
0
Table 2 - Control Register
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