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參數(shù)資料
| 型號： | MX812J |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動時效編解碼器DRAM的控制 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 115K |
| 代理商： | MX812J |
VSR CODEC with DRAM CONTROL
5
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
Application Information ......
Bank Select
Inputs
A
0
1
0
1
DRAM No 1
Pages
0 – 1023
DRAM No 2
Pages
1024 – 2047
B
0
0
1
1
Driving Two 4-MBit DRAM Sections
By adding external logic circuitry, the MX812 can be configured
to drive two 4-MBit DRAM sections. This will have the effect of
doubling the available storage time. i.e. 4 minutes at 32kbps.
With reference to the circuitry shown in Figure 5:
With the Mode Register
MS
Bit set to “0” the MX812 treats the
DRAM sections as two 1-Mbit devices. The external logic makes
each 4-MBit DRAM appear as four 1-MBit banks selected by the
Bank Select lines ‘
A
’ and ‘
B
.’
Figure 5 - Use of External Elements to Drive Two 4-MBit DRAM Chips
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D
WE
MX812
4Mbit.
DRAM
V
DD
V
SS
D
GND
V
CC
+ 5.0V
+ 5.0V
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q
D
CAS
1Mbit.
DRAM.
No.1
V
SS
V
CC
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q
D
CAS
V
SS
V
CC
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D
CAS
RAS1
A10/R2
MX812
V
DD
D
GND
1Mbit.
DRAM.
No.2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q
D
W
CAS
RAS
RAS
RAS
W
W
WE
CAS
RAS1
A10/R2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q
D
W
CAS
RAS
4Mbit
DRAM
No. 1
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D
WE
CAS
RAS1
A10/R2
MX812
4Mbit
DRAM
No. 2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q
D
W
CAS
RAS
A
B
BANK
SELECT
INPUTS
'HC04
'HC00
Choice of DRAM Devices
DRAM devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 Dynamic Random Access
memories, with ‘CAS before RAS’ refresh, and a Row Address access time of 200 nano-seconds or less.
Figure 4 - Example DRAM Connections
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