參數(shù)資料
型號(hào)： MX26F128J3XCC-12
廠商： Electronic Theatre Controls, Inc.
英文描述： Macronix NBit TM Memory Family 128M [x8/x16] SINGLE 3V PAGE MODE eLiteFlash TM MEMORY
中文描述： 旺宏NBit商標(biāo)家庭128M的內(nèi)存[x8/x16]單3V頁模式eLiteFlash商標(biāo)記憶
文件頁數(shù)： 39/47頁
文件大?。?/td> 439K
代理商： MX26F128J3XCC-12
39
P/N:PM0960
REV. 1.1,OCT. 18, 2004
MX26F128J3
AC Characteristics--Write Operations (1,2)
Versions
Valid for All
Speeds
Unit
Symbol
Parameter
Notes
Min
Max
tPHWL (tPHEL )
RESET High Recovery to WE(CEX) Going Low
3
210
ns
tELWL (tWLEL )
CEX (WE) Low to WE(CEX) Going Low
4
0
ns
tWP
Write Pulse Width
4
70
ns
tDVWH (tDVEH )
Data Setup to WE(CEX) Going High
5
50
ns
tAVWH (tAVEH )
Address Setup to WE(CEX) Going High
5
55
ns
tWHEH (tEHWH)
CEX (WE) Hold from WE(CEX) High
0
ns
tWHDX (tEHDX)
Data Hold from WE(CEX) High
0
ns
tWHAX (tEHAX)
Address Hold from WE(CEX) High
0
ns
tWPH
Write Pulse Width High
6
30
ns
tVPWH (tVPEH)
VPEN Setup to WE(CEX) Going High
3
0
ns
tWHGL (tEHGL)
Write Recovery before Read
7
35
ns
tWHRL (tEHRL)
WE(CEX) High to STS Going Low
8
500
ns
tQVVL
VPEN Hold from Valid SRD, STS Going High
3,8,9
0
ns
tWHQV5 (tEHQV5) Set Lock-Bit Time
4,9
64
75/85
us
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time
4
0.5
2
sec
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first
edge of CE0, CE1, or CE2 that disables the device (see Table 2).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
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