參數(shù)資料
型號： MVTX2802AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 網(wǎng)絡接口
英文描述： Managed 4-Port 1000 Mbps Ethernet Switch
中文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝： 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù)： 21/154頁
文件大?。?/td> 1936K
代理商： MVTX2802AG
MVTX2802
Data Sheet
21
Zarlink Semiconductor Inc.
3.2 Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to
drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the
frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some
subset of the multicast packet’s destinations. If so, then the frame is dropped at some destinations but not
others, and the FCB is not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the
multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast
frames). There are 4 multicast queues for each of the 4 Gigabit ports. During scheduling, the TxQ manager
treats the unicast queue and the multicast queue of the same class as one logical queue.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
3.3 Frame Forwarding To and From CPU
Frame forwarding
from
the CPU port to a regular transmission port is nearly the same as forwarding between
transmission ports. The only difference is that the physical destination port must be indicated in addition to the
destination MAC address. If an invalid port is indicated the frame is forwarded accordingly to the destination
MAC address.
Frame forwarding
to
the CPU port is nearly the same as forwarding to a regular transmission port. The only
difference is in frame scheduling. Instead of using the patent-pending scheduling algorithms, scheduling for
the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted
before a frame in a lower priority queue. There are four output queues to the CPU and one received queue.
4.0 Memory Interface
4.1 Overview
The figure below illustrates the first part of the ZBT-SRAM interface for the MVTX2802AG. As shown, a 64 bit
bus ZBT-SRAM bank A is used for Tx/RxDMA access. Because the clock frequency is 133 MHz, the total
memory bandwidth is 64 bits
×
133 MHz = 8.5 Gbps, for frame data buffer (FDB) access.
Not shown in the figure are the CPU port RxDMA’s and TxDMA’s, each separately connected to its own bank
selector.
Figure 4 - MVTX2802AG SRAM Interface Block Diagram (DMAs for Gigabit Ports)
ZBT-SRAM Bank A
TX DMA
0-1
RX DMA
0-1
RX DMA
2-3
TX DMA
2-3
相關PDF資料
PDF描述
MVTX2803 Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803AG Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2804 8-Port 1000 Mbps Ethernet Distributed Switch
MVTX2804AG 8-Port 1000 Mbps Ethernet Distributed Switch
MVV200 Analog IC
相關代理商/技術參數(shù)
參數(shù)描述
MVTX2803 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 8 port Gigabit Ethernet switch
MVTX2803AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803AG2 制造商:Microsemi Corporation 功能描述:
MVTX2804 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch
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