參數(shù)資料
型號: MVTX2603AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA553
封裝: 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
文件頁數(shù): 73/109頁
文件大?。?/td> 803K
代理商: MVTX2603AG
MVTX2603
Data Sheet
73
Zarlink Semiconductor Inc.
Bit [5] – Signal detect (when PCS interface mode)
Bit [6] – 2 G signal detect (2 G mode only)
Bit [7] – Module detected (for hot swap purpose)
13.9.6 PLLCR - PLL Control Register
CPU Address: hF05
Accessed by serial interface (RW)
Bit [3]
Must be '1'
Bit [7]
Selects strap option or LCLK/OECLK registers
0 - Strap option (default)
1 - LCLK/OECLK registers
13.9.7 LCLK - LA_CLK delay from internal OE_CLK
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10] LCLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay (Recommend)
100b 08h 4 Buffers Delay
101b 04h 3 Buffers Delay
110b 02h 2 Buffers Delay
111b 01h 1 Buffers Delay
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
13.9.8 OECLK - Internal OE_CLK delay from SCLK
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13] OECLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay (Recommend)
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay
100b 08h 4 Buffers Delay
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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