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MVTX2603
Data Sheet
11
Zarlink Semiconductor Inc.
1.5 Configuration Interface Module
The MVTX2603 supports a serial and an I
2
C interface, which provides an easy way to configure the system. Once
configured, the resulting configuration can be stored in an I
2
C EEPROM.
1.6 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.7 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2). It
also performs MAC learning, priority assignment and trunking functions.
1.8 LED Interface
The LED interface provides a serial interface for carrying 24+2 port status signals. It can also provide direct status
pins (6) for the two Gigabit ports.
1.9 Internal Memory
Several internal tables are required and are described as follows:
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc.
MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the
external MAC Table. The external MAC table is located in the FDB Memory.
Note:
the external MAC table is located in the external SBRAM Memory.
2.0 System Configuration
2.1 Configuration Mode
The MVTX2603 can be configured by EEPROM (24C02 or compatible) via an I
2
C interface at boot time, or via a
synchronous serial interface during operation.
2.2 I
2
C Interface
The I
2
C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
2 depicts the data transfer format.
Figure 2 - Data Transfer Format for I
2
C Interface
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP