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參數(shù)資料
| 型號： | MV1442IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDB3 Encoder/Decoder/Clock Regenerator |
| 中文描述： | 采用HDB3編碼器/解碼器/時鐘再生器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 726K |
| 代理商： | MV1442IG |
3
MV1442
B
B
B
V
4·5 CLOCK PERIODS
B
B
V
ENCODER
CLOCK
NRZ DATA IN
TXD1
TXD2
NOTES
1. The encoded HDB3 outputs, TXD1 and TXD2. are delayed dy 4·5 clock periods with respect to NRZ DATA IN.
2. B is an HDB3 mark, V is an HDB3 violation.
Figure 3 - Encoder waveforms
B
B
V
B
B
B
B
B
B
B
5 CLOCK PERIODS
RXD1
RXD2
NRZ DATA OUT
CDR
DECODER
CLOCK
NOTES
1. The decoded NRZ output is delayed by 5 clock periods with respect to the HDB3 inputs.
2. The diagram assumes the last violation occured on RXD2.
3. B is an HDB3 mark, V is an HDB3 violation.
Figure 4 - Decoder waveforms
B
B
V
B
V
B
B
B
1 CLOCK PERIOD
RXD1
RXD2
DECODER
CLOCK
NOTES
1. There is a single clock period delay from detection of an error and the rising edge of DOUBLE VIOLATION
2. The diagram assumes the last violation occured on RXD2.
3. B is an HDB3 mark, V is an HDB3 violation.
V
DOUBLE
VIOLATION
Figure 5 - HDB3 double violation waveforms
absence of input jitter the MV1442 will produce an output
jitter waveform in the form of a sawtooth ramping between
0UI and 0.125UI. The period of this waveform will be de-
pendent upon the difference in frequencies between the
remote transmitter’s clock and the crystal controlled clock of
the MV1442.
The MV1442 was originally designed as a pin compatible
replacement for the MV1441 with a much improved internal
clock recovery circuit and allowing operation at 8.448MHz
with external clock recovery selected.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MV1442IGDPAS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442IGMPES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442MPES | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:HDB3 Encoder/Decoder/Clock Regenerator |
| MV1443IGDGAS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| MV1443IGDPAS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
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