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參數(shù)資料
| 型號： | MV1442IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | HDB3 Encoder/Decoder/Clock Regenerator |
| 中文描述： | 采用HDB3編碼器/解碼器/時鐘再生器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 726K |
| 代理商： | MV1442IG |
2
MV1442
CLOCK
REGENERATOR
CRYSTAL
OUT/CDR
CRYSTAL
IN
ENCODER
NRZ
DATA IN
ENCODER
CLOCK
DECODER
ERROR
CIRCUIT
COUNTER
AIS CIRCUIT
MODE
RXD 1
LOOP TEST
ENABLE
RXD 2
TXD 1
TXD 2
DOUBLE VIOLATION
DECODER
CLOCK
LOSS OF
INPUT
NRZ DATA
OUT
AIS
RESET AIS
Functional Descriptions
High Density Bipolar 3 (HDB3) is a pseudo-ternary trans-
mission code in which the number of consecutive zeros
which may occur is restricted to three to allow adequate
clock recovery at the receiver. In any sequence of four
consecutive binary zeros the last zero is substituted by a
mark of the same polarity as the previous mark, thus break-
ing the Alternate Mark Inversion (AMI) code. This mark is
termed a violation. In addition, the first zero may also be
substituted by a mark if the last mark and last violation are of
the same polarity. This mark does not violate the AMI code
and ensures that successive violations alternate in polarity
and as such introduce no DC component to the HDB3 signal.
The MV1442 consists of three main blocks: the HDB3
Encoder, the HDB3 Decoder and the Clock Regenerator.
The function of each block is now described separately.
HDB3 Encoder
The HDB3 Encoder is responsible for converting the
incoming NRZ data into pseudo-ternary form for transmis-
sion over a PCM link. This conversion is carried out in
accordance with the HDB3 coding laws specified in CCITT
Recommendation G. 703 The data to be encoded is input on
the NRZ DATA IN pin and the encoding process is synchro-
nised to the clock signal being input on the ENCODER
CLOCK pin. The two TXD outputs TXD1 and TXD2. repre-
sent the HDB3 data in pseudo-ternary form. If a mark is to be
transmitted, the output goes high after the rising edge of the
clock. The length of the pulse is set by the positive clock
pulse width. The timing diagram of the HDB3 Encoder is
shown in Figure 3.
HDB3 Decoder
The HDB3 Decoder is responsible for decoding the HDB3
pseudo-ternary data on its inputs RXD1 and RXD2 into NRZ
form to be output on the NRZ DATA OUT pin. In addition to
this, the decoder circuit provides three alarm outputs. The
first of these alarms is DOUBLE VIOLATION. As its name
suggests, a logic high on this output denotes that two
successive violations have been received with the same
polarity, thus violating the HDB3 coding laws. The second
alarm, LOSS OF INPUT, is used to denote that 11 consecu-
tive zeros have been received on the RXD inputs. The final
alarm output is AIS (all ones) This alarm goes high if less
than 3 decoded zeros have been detected in the preceding
RESET AIS = 1 period (i.e. between RESET AIS = 0 pulses)
and as such this alarm can be used as an ‘a(chǎn)ll ones’ detector.
The decoding process and all the alarm circuitry is synchro-
nised to the clock signal being input to this block on the
DECODER CLOCK pin. This clock signal may be asynchro-
nous with the ENCODER CLOCK signal. The timing dia-
grams of the HDB3 Decoder and alarm circuitry are shown
in Figures 4 to 7.
In addition to the normal mode of operation, a loop test
mode is available for terminal testing. This mode is selected
by taking the LOOP TEST ENABLE input high. In this mode
the HDB3 encoded pseudo-ternary data outputs of the
Encoder block are fed back as the inputs to the Decoder
block, which in turn decodes this data and outputs it in NRZ
form.
Clock Regenerator
The Clock Regenerator block has two possible modes of
operation. With the MODE pin high, internal crystal control-
led clock regeneration is selected, whereas with the MODE
pin low external clock regeneration is selected using, for
example, a tuned circuit.
In external clock regeneration mode, a logically ORed
version of the HDB3 data, from the RXD inputs, is output to
the external clock regeneration circuitry on the CRYSTAL
OUT/CDR pin. The regenerated clock is then fed back into
the MV1442 on the DECODER CLOCK pin External clock
regeneration may be used for operation with data rates of
1.544Mbits, 2.048Mbits or 8.448Mbits.
In internal clock regeneration mode, the logically ORed
data is input to a digital regenerator which constantly
resynchronises a divide-by-8 counter to the incoming data
stream. The clock thus regenerated is output to the de-
coder circuitry and to any external circuitry on the
DECODER CLOCK pin. A crystal of frequency 8 times the
required data rate must be connected between the
CRYSTAL IN and CRYSTAL OUT/CDR pins. Thus, the
crystal frequency needs to be 16.384MHz or 12.352MHz
for data rates of 2.048Mbits or 1.544Mbits respectively.
Internal clock regeneration may not be used for operation
at a data rate of 8.448Mbits.
The MV1442 is capable of withstanding up to 0.25UI of
peak to peak input jitter at a jitter frequency of 2.048MHz
without introducing errors into the decoded data. At lower
jitter frequencies the MV1442 is capable of withstanding
much larger values to peak to peak input jitter. In the
Figure 2 - Block diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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| MV1442IGDPAS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442IGMPES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Encoder/Decoder |
| MV1442MPES | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:HDB3 Encoder/Decoder/Clock Regenerator |
| MV1443IGDGAS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
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