Semiconductor Components Industries, LLC, 2006
September, 2006 Rev. 17
Publication Order Number:
MUN2111T1/D
1
MUN2111T1 Series
Preferred Devices
Bias Resistor Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The
Bias Resistor Transistor (BRT) contains a single transistor with a
monolithic bias network consisting of two resistors; a series base
resistor and a baseemitter resistor. The BRT eliminates these
individual components by integrating them into a single device. The
use of a BRT can reduce both system cost and board space. The device
is housed in the SC59 package which is designed for low power
surface mount applications.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Moisture Sensitivity Level: 1
ESD Rating Human Body Model: Class 1
Machine Model: Class B
The SC59 Package Can be Soldered Using Wave or Reflow
The Modified GullWinged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
PbFree Packages are Available
MAXIMUM RATINGS
(T
A
= 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector Base Voltage
V
CBO
50
Vdc
Collector Emitter Voltage
V
CEO
50
Vdc
Collector Current
I
C
100
mAdc
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation
T
= 25
°
C
Derate above 25
°
C
P
D
230 (Note 1)
338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
mW
°
C/W
Thermal Resistance,
JunctiontoAmbient
R
JA
540 (Note 1)
370 (Note 2)
°
C/W
Thermal Resistance,
JunctiontoLead
R
JL
264 (Note 1)
287 (Note 2)
°
C/W
Junction and Storage Temperature
Range
T
J
, T
stg
55 to +150
°
C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR4 @ Minimum Pad.
2. FR4 @ 1.0 x 1.0 inch Pad.
SC59
CASE 318D
PLASTIC
MARKING DIAGRAM
PIN 3
COLLECTOR
(OUTPUT)
PIN 1
EMITTER
(GROUND)
PIN 2
BASE
(INPUT)
R1
R2
2
1
3
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
See device marking table on page 2 of this data sheet.
DEVICE MARKING INFORMATION
Preferred
devices are recommended choices for future use
and best overall value.
http://onsemi.com
1
6x M
6x
M
= Specific Device Code
= Date Code*
= PbFree Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.