- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359236 > MU9C1480L-12DC Content Addressable Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | MU9C1480L-12DC |
| 英文描述： | Content Addressable Memory |
| 中文描述： | 內(nèi)容可尋址存儲(chǔ)器 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 246K |
| 代理商： | MU9C1480L-12DC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
MU9C1480A/L Draft
Rev. 3.0 Draft
17
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
f
Address Field flag
sss
Selected source
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source will be at aaaH, after
which the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
Address Field flag
mm
Mask Register select
ddd
Selected destination
vvv
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction changes
it or a reset occurs. The default destination for Data Write
cycles is the Comparand register after a reset. When the
destination is the Comparand register or the Memory array,
the data written may be masked by either Mask Register 1
or Mask Register 2, so that only destination bits
corresponding to bits in the mask register set to 0 will be
modified. An automatic compare will occur after writing the
last segment of the Comparand or mask registers, but not
after writing to Memory. Setting the persistent destination
to M@aaaH loads the Address register with “aaaH,” and
the first access to that persistent destination will be at aaaH,
after which the AR value increments or decrements as set in
the Control register. The SPD M@[AR] instruction does
the same except the current Address Register value is used.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write cycle,
so a value can be loaded or read out of the register.
Subsequent Command Read or Write cycles revert to
reading the Status register and writing to the Instruction
decoder. All registers but the NF, PS, and PD can be written
to, and all can be read from. The Status register is only
available through non-TCO Command Read cycles.
Reading the PS register also outputs the Device ID on bits
15–4 as shown in Table 12 on page 22.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
f
Address Field flag
mm
Mask Register select
ddd
Destination of data
sss
Source of data
v
Validity setting if destination is a
Memory location
The MOV instruction performs a 64-bit move of the data in
the selected source to the selected destination. If the
source or destination is aaaH, the Address register is set
to “aaaH.” For MOV instructions to or from aaaH or [AR],
the Address register will increment or decrement from that
value after the move completes, as set in the Control
register. Data transfers between the Memory array and the
Comparand register may be masked by either Mask
Register 1 or Mask Register 2, in which case, only those
bits in the destination that correspond to bits in the selected
mask register set to 0 will be changed. A Memory location
used as a destination for a MOV instruction may be set to
Valid or left unchanged. If the source and destination are
the same register, no net change occurs
(a NOP).
Instruction: Validity Bit Control (VBC)
Binary Op-Code: 0000 f100 00dd dvvv
f
Address Field flag
ddd
Destination of data
vvv
Validity setting for Memory location
The VBC instruction sets the Validity bits at the selected
memory locations to the selected state. This feature can be
used to find all valid entries by using a repetitive sequence
of CMP V through a mask of all 1s followed by a VBC HM, S.
If the VBC target is aaaH, the Address register is set to
“aaaH.” For VBC instructions to or from aaaH or [AR], the
Address register will increment or decrement from that value
after the operation completes, as set in the Control register.
INSTRUCTION SET DESCRIPTIONS*
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MU9C1480L-12DI | Content Addressable Memory |
| MU9C1480L-70DC | Content Addressable Memory |
| MU9C1480L-70DI | Content Addressable Memory |
| MU9C1480L-90DC | Content Addressable Memory |
| MU9C1480L-90DI | Content Addressable Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MU9C1480L-12DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM) |
| MU9C1480L-70DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480L-70DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480L-90DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480L-90DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。