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| 型號： | MU9C1480B-90TAC |
| 英文描述： | Content Addressable Memory |
| 中文描述： | 內(nèi)容可尋址存儲器 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 246K |
| 代理商： | MU9C1480B-90TAC |
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MU9C1480A/L Draft
Rev. 3.0 Draft
12
Move commands (MOV). Moves using the Comparand
register can also be masked by either of the mask registers.
I/O CYCLES
The LANCAM supports four basic I/O cycles: Data Read,
Data Write, Command Read, and Command Write. The states
of the /W and /CM control inputs determine the type of
cycle. These signals are registered at the beginning of a
cycle by the falling edge of /E. Table 2 on page 2 shows
how the /W and /CM signals select the cycle type.
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
the cycle by the falling edge of /E. Figures 3 and 4 on page
13, show Read and Write cycles respectively. Figure 5 on
page 13, shows typical cycle-to-cycle timing with the Match
flag valid at the end of the Comparand Write. Data writes
and reads to the comparand, mask registers, or memory
occur in one to four 16-bit cycles, depending on the settings
in the Segment Control register. The Compare operation
automatically occurs during Data writes to the Comparand
or mask registers when the destination segment counter
reaches the end count set in the Segment Control register.
If there was a match, the second cycle reads status or
associated data, depending on the state of /CM. For
cascaded devices, /EC needs to be LOW at the start of the
cycle prior to any cycle that requires a locked daisy chain,
such as a Status register or associated data read after a
match. If there is no match in Standard mode, the output
buffers stay High-Z, and the daisy chain must be unlocked
by taking /EC HIGH during a NOP or other non-functioning
cycle, as indicated in Table 5a. Figure 6 on page 14 shows
how the internal /EC timing holds the daisy chain locking
effect over into the next cycle. In Enhanced mode, this
NOP is not needed before data or command writes following
a non-matching compare, as indicated by Table 5b. A
single-chip system does not require daisy-chained match
flag operation, hence /EC could be tied HIGH and the
/MA pin or flag in the Status register used instead of
/MF, allowing access to the device regardless of the
match condition.
The minimum timings for the /E control signal are given in
the Switching Characteristics section on page 25. Note that
at minimum timings the /E signal is non-symmetrical and
that different cycle types have different timing requirements,
as given in Table 7 on page 21.
COMPARE OPERATIONS
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any mask register used during compares
must be selected beforehand in the Control register. There
are two ways compares are initiated: Automatic compare
and Forced compare.
Automatic compares perform a compare of the contents of the
Comparand register against Memory locations that are tagged
as “Valid,” and occur whenever the following happens:
The Destination Segment counter in the Segment
Control register reaches its end limit during writes to
the Comparand or mask registers.
After a command write of a TCO CT is executed (except
for a software reset), so that a compare is executed
with the new settings of the Control register.
Forced compares are initiated by CMP instructions
using one of the four validity conditions: V, R, S, and E. The
forced compare against “Empty” locations automatically
masks all 64 bits of data to find all locations with the validity
bits set to “Empty,” while the other forced compares are
only masked as selected in the Control register.
VERTICAL CASCADING
LANCAMs can be vertically cascaded to increase system
depth. Through the use of flag daisy-chaining, multiple
devices will respond as an integrated system. The flag daisy
chain allows all commands to be issued globally, with a
response only in the device containing the
Highest-Priority Matching or Next Free location. When
connected in a daisy chain, the last device’s Full flag and
Match flag accurately report the condition for the whole
string. A system in which LANCAMs are vertically
cascaded using daisy-chaining of the flags is shown in
Figure 1a on page 7.
To operate the daisy chain, the Device Select registers are
set to FFFFH to enable all devices to execute Command
Write and Data Write cycles. In normal operation, read
cycles are enabled from the device with the Highest-Priority
match by locking the daisy chain (see the “Locked Daisy
Chain” section). An individual device in the chain may be
targeted for a read or write operation by temporarily setting
the Device Select registers to the Page address of the target
device. Setting the Device Select registers back to FFFFH
restores the operation of the entire daisy chain.
OPERATIONAL CHARACTERISTICS Continued
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MU9C1480B-90TAI | Content Addressable Memory |
| MU9C1480L-12DC | Content Addressable Memory |
| MU9C1480L-12DI | Content Addressable Memory |
| MU9C1480L-70DC | Content Addressable Memory |
| MU9C1480L-70DI | Content Addressable Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MU9C1480B-90TAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480L | 制造商:MUSIC 制造商全稱:MUSIC Semiconductors 功能描述:TQFP Package Option |
| MU9C1480L-12DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480L-12DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The 1024 x 64-bit LANCAM facilitates numerous 1024 x 64-bit CMOS content-addressable memory (CAM) |
| MU9C1480L-70DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
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