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參數(shù)資料
| 型號(hào)： | MTP50P03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS RDS(on) = 0.025 OHM |
| 中文描述： | 50 A, 30 V, 0.025 ohm, P-CHANNEL, Si, POWER, MOSFET, TO-220AB |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MTP50P03HDL |
1
Motorola, Inc. 1997
P–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
VDGR
VGS
VGSM
30
Vdc
Drain–Gate Voltage (RGS = 1.0 M
)
Gate–Source Voltage — Continuous
— Non–Repetitive (tp
≤
10 ms)
30
Vdc
±
15
±
20
Vdc
Vpk
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
ID
ID
IDM
50
31
150
Adc
Apk
Total Power Dissipation
Derate above 25
°
C
PD
125
1.0
Watts
W/
°
C
Operating and Storage Temperature Range
TJ, Tstg
EAS
–55 to 150
°
C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25
)
1250
mJ
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient, when mounted with the minimum recommended pad size
R
θ
JC
R
θ
JA
1.0
62.5
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
TL
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTP50P03HDL/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
RDS(on) = 0.025 OHM
Motorola Preferred Device
CASE 221A–06, Style 5
TO–220AB
D
S
G
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTP50P03HDLG | 功能描述:MOSFET PFET T0220 30V 50A 25mOhm RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| MTP50P03HDLG | 制造商:ON Semiconductor 功能描述:MOSFET P TO-220 |
| MTP50S | 制造商:NELLSEMI 制造商全稱:Nell Semiconductor Co., Ltd 功能描述:Three-Phase Bridge Rectifier, 50A |
| MTP50W | 制造商:NELLSEMI 制造商全稱:Nell Semiconductor Co., Ltd 功能描述:Glass Passivated Triple-Phase Bridge Rectifier, 50A |
| MTP5210F3 | 制造商:CYSTEKEC 制造商全稱:Cystech Electonics Corp. 功能描述:P-Channel Enhancement Mode Power MOSFET |
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