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參數(shù)資料
| 型號(hào)： | MTD20P03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 19 AMPERES 30 VOLTS RDS(on) = 0.099 OHM |
| 中文描述： | 19 A, 30 V, 0.099 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 244K |
| 代理商： | MTD20P03HDL |
8
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.190
4.826
mm
inches
0.100
2.54
0.063
1.6
0.165
4.191
0.118
3.0
0.243
6.172
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R
θ
JA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =
TJ(max) – TA
R
θ
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25
°
C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.
PD =
150
°
C – 25
°
C
71.4
°
C/W
= 1.75 Watts
The 71.4
°
C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R
θ
JA versus drain pad area is shown in Figure 16.
Figure 16. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
1.75 Watts
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25
°
C
A, AREA (SQUARE INCHES)
T
°
R
θ
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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| MTD20P03HDL1 | 制造商:ON Semiconductor 功能描述:Trans MOSFET P-CH 30V 19A 3-Pin(3+Tab) IPAK Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MTD20P03HDL1G | 制造商:ON Semiconductor 功能描述:Trans MOSFET P-CH 30V 19A 3-Pin(3+Tab) IPAK Rail |
| MTD20P03HDLT4 | 功能描述:MOSFET P-CH 30V 19A DPAK RoHS:否 類別:分離式半導(dǎo)體產(chǎn)品 >> FET - 單 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金屬氧化物 FET 特點(diǎn):邏輯電平門 漏極至源極電壓(Vdss):200V 電流 - 連續(xù)漏極(Id) @ 25° C:18A 開態(tài)Rds（最大）@ Id, Vgs @ 25° C:180 毫歐 @ 9A，10V Id 時(shí)的 Vgs(th)（最大）:4V @ 250µA 閘電荷(Qg) @ Vgs:72nC @ 10V 輸入電容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安裝類型:通孔 封裝/外殼:TO-220-3 整包 供應(yīng)商設(shè)備封裝:TO-220FP 包裝:管件 |
| MTD20P06 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:TMOS POWER FET LOGIC LEVEL 15 AMPERES 60 VOLTS RDS(on) = 175 MOHM |
| MTD20P06HDL | 制造商:ON Semiconductor 功能描述:MOSFET P LOGIC D-PAK |
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