參數(shù)資料
型號(hào): MT9VDDT3272A
廠商: Micron Technology, Inc.
英文描述: DDR SDRAM DIMM
中文描述: DDR SDRAM的內(nèi)存
文件頁(yè)數(shù): 21/29頁(yè)
文件大小: 542K
代理商: MT9VDDT3272A
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
21
2003 Micron Technology. Inc.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41.
42. For -335, -262, -26A, and -265 speed grades, I
DD
3N
is specified to be 35mA x (# of DDR SDRAM
devices) at 100 MHz.
43. Random addressing changing and 50 percent of
data changing at every transfer.
44. Random addressing changing and 100 percent of
data changing at every transfer.
45. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
t
RAP
t
RCD.
46. I
DD
2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to I
DD
2F except I
DD
2Q specifies the address and
control inputs to remain stable. Although IDD2F,
I
DD
2N, and I
DD
2Q are similar, I
DD
2F is “worst
case.”
47. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
48. Min
t
CK value at CL=2.5 in the SPD for and -26A
speeds is 0.7ns, to facilitate proper system opera-
tion.
49. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
50. The -335 module speed grade, using the -6R speed
device, has V
DD
(MIN) = 2.4V.
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