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參數(shù)資料
| 型號： | MT9KDF12872PZ-1G6XX |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | HALOGEN FREE, MO-269, RDIMM-240 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 401K |
| 代理商： | MT9KDF12872PZ-1G6XX |
Table 6: Pin Descriptions
Symbol
Type
Description
A[15:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selec-
ted by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS
commands. The address inputs also provide the op-code during the mode register com-
mand set. A[13:0] address the 1Gb DDR3 devices. A[14:0] address the 2Gb DDR3 devices.
A15 is needed to calculate parity on the command/address bus.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are used
as part of the parity calculation.
CK0, CK0#
Input
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKE0
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
DM[8:0]
(TDQS[17:9]
TDQS#[17:9])
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins. When TDQS is enabled, DM is disabled and TDQS
and TDQS# provide termination resistance; otherwise, the TDQS# pins are no function.
ODT0
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DRAM. When enabled in normal operation, ODT is only
applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if
disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver is
a CMOS input defined as a rail-to-rail signal with DC HIGH
≥ 0.8 × Vdd and DC LOW ≤ 0.2 ×
Vdd. RESET# assertion and deassertion are asynchronous. System applications will most like-
ly be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate
receiver design is recommended along with implementing on-chip noise filtering to pre-
vent false triggering (RESET# assertion minimum pulse width is 100ns).
S0#
Input
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command de-
coder.
SA[2:0]
Input
Serial address inputs: These pins are used to configure the temperature sensor/SPD EE-
PROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM.
CB[7:0]
I/O
Check bits: Data used for ECC.
DQ[63:0]
I/O
Data input/output: Bidirectional data bus.
1GB, 2GB (x72 SR) 240-Pin Halogen-Free 1.35V DDR3 RDIMM
Pin Assignments and Descriptions
PDF: 09005aef83c0f177
kdf9c128_256x72pz.pdf – Rev. A 08/09
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9KDF25672AZ-1G4K1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR3 SDRAM MODULE COMMERCIAL PBF VLPDIMM GREEN 1 - Bulk 制造商:Micron Technology Inc 功能描述:MODULE DDR3 2GB EUDIMM |
| MT9KDF25672PZ-1G1D1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR3 SDRAM MODULE PBF VLPDIMM GREEN 1.35V REG - Trays |
| MT9KDF25672PZ-1G4D1 | 功能描述:MODULE DDR3 SDRAM 2GB 240RDIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT9KDF25672PZ-1G4DZES | 制造商:Micron Technology Inc 功能描述:MT9KDF25672PZ-1G4DZES - Trays |
| MT9KDF25672PZ-1G4H1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR3 SDRAM MODULE PBF DIMM GREEN 1.35V REGISTERE - Trays |
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