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參數(shù)資料
| 型號： | MT93L04 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | 128頻道語音回聲消除器 |
| 文件頁數(shù)： | 8/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04 |
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MT93L04
Data Sheet
8
Zarlink Semiconductor Inc.
Sg1_d1
ICO
E4
Internal Connection.
Connected to VSS for
normal operation
DT1_d1
NC
F3
No connection.
The pin must be left open for
normal operation.
MCLK_d1
User Signal
E2
Master Clock (Input).
Nominal 10 MHz or
20 MHz Master Clock input. May be connected to
an asynchronous (relative to frame signal) clock
source.
Fsel_d1
User Signal
D1
Frequency select (Input).
This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2 MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6 MHz Master Clock input must be applied.
Halt_d1
ICO
E1
Internal Connection.
Connected to VSS for
normal operation
Step_d1
ICO
F2
Internal Connection.
Connected to VSS for
normal operation
PLLVSS1_d1
Power
G3
PLL Ground.
Must be connected to VSS
PLLVDD_d1
Power
F1
PLL Power Supply.
Must be connected to VDD2
PLLVSS2_d1
Power
G2
PLL Ground.
Must be connected to VSS
AT1_d1
NC
G1
No connection.
The pin must be left open for
normal operation.
DEVICE 2
TMS_d2
Signal
V4
Test Mode Select (3.3 V Input).
JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
TDI_d2
Signal
Y2
Test Serial Data In (3.3 V Input).
JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
TDO_d2
Signal
W3
Test Serial Data Out (Output).
JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
TCK_d2
Signal
Y3
Test Clock (3.3 V Input).
Provides the clock to
the JTAG test logic.
TRSTB_d2
Signal
W4
Test Reset (3.3 V Input).
Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Pin Description (continued)
Signal Name
Signal Type
BGA Ball #
Signal Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT93L04A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller |
| MT93L04AG | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L04AG2 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L16 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
| MT93L16AF | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 48TQFP - Rail/Tube |
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