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參數(shù)資料
| 型號(hào)： | MT93L04 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | 128頻道語音回聲消除器 |
| 文件頁數(shù)： | 46/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04 |
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MT93L04
Data Sheet
46
Zarlink Semiconductor Inc.
Bit
Name
Description
7-5
unused
Unused Bits.
4
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
3
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
2
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, select sign-magnitude
PCM code
.
1
LAW
A/
μ
Law: When high, both Echo Cancellers A and B for a given group, select A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, select m-Law companded
PCM code
.
0
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given
group, are active.
When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed
from Rin to Rout and from Sin to Sout with two frames delay.
When the PWUP bit toggles from zero to one, the echo cancellers A and B execute
their initialization routine which presets their registers, Base Address+00H to Base
Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients.
Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for
their specific application.
Bit
Name
Description
7
IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt
FIFO register is read.
Logic Low indicates that no interrupt is pending and the FIFO is empty.
6:5
0
Unused bits. Always zero
Interrupt FIFO Register
I0
I1
I2
I3
I4
0
0
IRQ
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
Read Address:
410
H
(Read only)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT93L04A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller |
| MT93L04AG | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L04AG2 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L16 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
| MT93L16AF | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 48TQFP - Rail/Tube |
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