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參數(shù)資料
| 型號(hào)： | MT92220 |
| 廠(chǎng)商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | 1023 Channel Voice Over IP/AAL2 Processor |
| 中文描述： | ATM NETWORK INTERFACE, PBGA608 |
| 封裝： | 31 X 31 MM, 2.50 MM HEIGHT, MS-034, EPBGA-608 |
| 文件頁(yè)數(shù)： | 133/210頁(yè) |
| 文件大?。?/td> | 1536K |
| 代理商： | MT92220 |
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Data Sheet
MT92220
133
Zarlink Semiconductor Inc.
:
Figure 73 - Buffer Tag Format
The TX Channel Association Memory entry points to an entry in the TX TDM Control Memory that will define either
a PCM buffer or an HDLC stream. If the entry defines a PCM buffer, it will define the compression type of the data
to be received. The MT92220 can support TDM data in PCM A-law, PCM u-law, ADPCM-40, ADPCM-32,
ADPCM-24 and ADPCM-16 formats. It can also perform auto-detection of the compression rate received using
encoded values. Lastly, the TX TDM can perform law-translation on the incoming PCM values. The data can enter
as either u-law or A-law and can also exit as either u-law or A-law, with any translation between the two.
If the TX TDM Control Memory entry defines an HDLC stream, then the entry will contain information used to
perform HDLC de-framing. Many fields are used to keep byte-per-byte context. The entry also contains fields
specifying the HDLC header format: the chip supports HDLC addresses of 0, 1 or 2 bytes, as well as 0 or 1 HDLC
control bytes. Each HDLC packet may also be trailed by a 16-bit CRC, configurable per stream. The HDLC
addresses are used to distinguish multiple channels on the same HDLC stream, with a maximum of 512 channels
per stream (using the 9 low bits of a 2-byte address), or a maximum of 256 channels when using a single-byte
address.
The TX Channel Association Memory also has an AS (Associated Stream) bit that allows greater bandwidth on
HDLC streams. When this bit is ‘1’, the TX Channel Association Memory binds 2 time slots to the corresponding TX
TDM Control Memory entry instead of 1. This increases the total capacity of the TX Data Path in HDLC mode to
2046 time slots. In this mode, the 2 time slots that are bound together are 2 adjacent H.110 streams (i.e.
ct_d
[0]
and
ct_d
[1], during the same time slot). The even stream contains the data that is logically first.
Each HDLC stream is associated to a circular buffer, of varying size depending on the maximum packet size
expected on that stream and the bandwidth of the stream. The circular buffer sizes can vary between 512 bytes and
32K bytes, in increments of 2
n
.
Field
Description
Stream/Buffer
Tag
Encoded field that points either to the TX TDM Control memory (for xxPCM Buffer and HDLC
stream) or to the Low-Latency Loopback Memory for Low-Latency Loopback channels.
AS
Associated Stream. When set, the least significant bit of the TSST number will be ignored and
both even and odd streams pointed to by the TSST number will be read for valid data. For
xxPCM circular buffers, the extra stream allows PCM / ADPCM codec changes to occur
smoothly. For HDLC streams, the extra stream doubles the bandwidth that is available on the
HDLC stream.
TSST
Time / Stream Number. TSST[11:5] represents the timeslot on which the data belonging to an
HDLC stream or to an xxPCM buffer will be received from. TSST[4:0] represents the stream
on which the data belonging to an HDLC stream or to an xxPCM buffer will be received from.
Link to next
entry
Pointer to the next TX Channel Association Memory Entry. Entries must be sorted according
to TSST number. Entry 0 is never considered to contain a Buffet Tag; it’s TSST is hardcoded
in the chip as number -1, which means that the last TX Channel Association Memory Entry
must point back to Entry 0 to be ready for the next frame.
Table 56 - Fields and Description
b8
b9
b10
b0
b1
b2
b3
b4
b5
b6
b7
1
PCM Buffer Number [9:0]
b8
b9
b10
b0
b1
b2
b3
b4
b5
b6
b7
0
HDLC Stream Number [8:0]
1
b8
b9
b10
b0
b1
b2
b3
b4
b5
b6
b7
0
0
0
1
LLL Buffer Number [6:0]
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