參數(shù)資料
型號(hào): MT9171
廠商: Mitel Networks Corporation
英文描述: Digital Subscriber Interface Circuit with RxSB(數(shù)字用戶接口電路(帶接收同步位))
中文描述: 數(shù)字用戶接口電路(數(shù)字用戶接口電路與RxSB(帶接收同步位))
文件頁(yè)數(shù): 3/25頁(yè)
文件大小: 209K
代理商: MT9171
Advance Information
MT9171/72
9-117
13
14
16
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
14
15
17
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device
to allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
15
16
19
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
Oscillator Output
. CMOS Output.
Oscillator Input
. CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1
’,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When
logic ’0’, the L
OUT
to the precanceller path is enabled and functions normally. An
internal pulldown (50 k
) is provided on this pin.
No Connection.
Leave open circuit
16
17
17
19
21
22
OSC2
OSC1
18
20
23
Precan
8,
18
1,6,
11,
18,
20,
25
24
NC
19
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 k
) is provided on this
pin.
TEST
Test Pin.
Connect to V
SS
.
L
IN
Receive Signal
input (Analog).
V
DD
Positive Power Supply
(+5V) input.
20
21
22
22
23
24
26
27
28
Pin Description (continued)
Pin #
Name
Description
22
24
28
相關(guān)PDF資料
PDF描述
MT9172 Digital Network Interface Circuit with RxSB(數(shù)字網(wǎng)絡(luò)接口電路(帶接收同步位))
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