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MT91L60/61
Data Sheet
18
Zarlink Semiconductor Inc.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
CEn
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the
channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h)
regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo.
The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on
DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has
significance only for ST-BUS mode and is ignored for SSI operation.
When high, D-channel operates at 8 kb/s. When low, D-channel operates at 16 kb/s (default).
When high, A-Law encoding/decoding is selected for the MT91L60/61. When low,
μ
-Law encoding/decoding is selected.
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is
selected for the Codec input/output; true sign, inverted magnitude (
μ
-Law) or true sign, alternate digit inversion (A-Law).
DEn
D8
A/
μ
Smag/ITU-T
CSL
2
CSL
1
CSL
0
Bit Clock rate (kHz)
CLOCKin (kHz)
Mode
1
1
1
N/A
4096
ST-BUS
1
0
0
128
4096
SSI
1
0
1
256
4096
SSI
0
0
0
512
512
SSI
0
0
1
1536
1536
SSI
0
1
0
2048
2048
SSI (default)
0
1
1
4096
4096
SSI
Control Register 2
ADDRESS = 04h WRITE/READ VERIFY
Power Reset Value
0000 0010
7
6
5
4
3
2
1
0
CEn
DEn
CSL
1
CSL
0
D8
A/
μ
CSL
2
Smag/
ITU-T