參數(shù)資料
型號(hào): MT9160AN1
廠商: Zarlink Semiconductor Inc.
元件分類: Codec
英文描述: 3 Volt Multi-Featured Codec (MFC)
中文描述: 3伏多精選編解碼器(MFC)中
文件頁數(shù): 11/33頁
文件大?。?/td> 527K
代理商: MT9160AN1
MT91L60/61
Data Sheet
11
Zarlink Semiconductor Inc.
When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on
DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high.
Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state.
When low, data transmission is halted and this timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and
transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel
(Control Register 1, address 03h) are used for this purpose.
If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR
control bits, Control Register 1 address 03h).
Figure 7a - D-Channel 16 kb/s Operation
Figure 7b - IRQ Timing Diagram
n-3
n-2
n-1
n
n+1
n+2
n+3
n+4*
Microport Read/Write Access
D0
D1
I
D2
D3
II
D4
D5
III
D6
Di-bit Group
Transmit
D-Channel
D7
IV
D0
D1
I
D2
Power-up reset to 1111 1111
D3
II
D4
D5
III
D6
D7
IV
No preset value
* note that frame n+4 is equivalent to frame n of the next cycle.
IRQ
FP
DSTo/
DSTi
Di-bit Group
Receive
D-Channel
Microport Read/Write Access
t
ir
=500 nsec max
R
pullup
= 10 k
t
if
=500 nsec max
D0
D1
Reset coincident with
Read/Write of Address 04 Hex
or next FP, whichever occurs first
FP
C4i
C2
IRQ
8 kb/s operation
16 kb/s operation
DSTo/
DSTi
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